cnt10.vhd

来自「数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
    port(clk:in std_logic;
         clr:in std_logic;
         ena:in std_logic;
         cq:out std_logic_vector(3 downto 0);
         carry_out:out std_logic);
 end entity cnt10;
architecture art of cnt10 is
   signal cqi,cqh:std_logic_vector(3 downto 0);
   begin
     process(clk,clr,ena)is
       begin 
        if clr='1' then cqi<="0000";
           elsif clk'event and clk='1' then
             if ena='1' then
                if cqi="1001"then 
                  cqi<="0000";
                  else cqi<=cqi+1;
                 end if;
              end if;
         end if;
       end process;
       process(cqi) is
         begin 
           if cqi="0000" then carry_out<='1';
              else carry_out<='0';
           end if;
       end process;
       cq<=cqi;
 end architecture art;