📄 miaobiao.rpt
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Device-Specific Information: d:\zhangshuhua\szmb\miaobiao.rpt
miaobiao
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
10 - - - 01 OUTPUT 0 1 0 0 dout0
18 - - A -- OUTPUT 0 1 0 0 dout1
11 - - - 01 OUTPUT 0 1 0 0 dout2
9 - - - 02 OUTPUT 0 1 0 0 dout3
39 - - - 11 OUTPUT 0 1 0 0 dout4
19 - - A -- OUTPUT 0 1 0 0 dout5
3 - - - 12 OUTPUT 0 1 0 0 dout6
17 - - A -- OUTPUT 0 1 0 0 dout7
51 - - - 18 OUTPUT 0 1 0 0 dout8
50 - - - 17 OUTPUT 0 1 0 0 dout9
72 - - A -- OUTPUT 0 1 0 0 dout10
70 - - A -- OUTPUT 0 1 0 0 dout11
69 - - A -- OUTPUT 0 1 0 0 dout12
47 - - - 14 OUTPUT 0 1 0 0 dout13
83 - - - 13 OUTPUT 0 1 0 0 dout14
61 - - C -- OUTPUT 0 1 0 0 dout15
49 - - - 16 OUTPUT 0 1 0 0 dout16
48 - - - 15 OUTPUT 0 1 0 0 dout17
71 - - A -- OUTPUT 0 1 0 0 dout18
58 - - C -- OUTPUT 0 1 0 0 dout19
52 - - - 19 OUTPUT 0 1 0 0 dout20
53 - - - 20 OUTPUT 0 1 0 0 dout21
28 - - C -- OUTPUT 0 1 0 0 dout22
23 - - B -- OUTPUT 0 1 0 0 dout23
59 - - C -- OUTPUT 0 0 0 0 duan0
7 - - - 03 OUTPUT 0 1 0 0 duan1
8 - - - 03 OUTPUT 0 1 0 0 duan2
6 - - - 04 OUTPUT 0 1 0 0 duan3
81 - - - 22 OUTPUT 0 1 0 0 duan4
60 - - C -- OUTPUT 0 1 0 0 duan5
54 - - - 21 OUTPUT 0 1 0 0 duan6
79 - - - 24 OUTPUT 0 1 0 0 duan7
62 - - C -- OUTPUT 0 1 0 0 wei0
24 - - B -- OUTPUT 0 1 0 0 wei1
65 - - B -- OUTPUT 0 1 0 0 wei2
67 - - B -- OUTPUT 0 1 0 0 wei3
64 - - B -- OUTPUT 0 1 0 0 wei4
25 - - B -- OUTPUT 0 1 0 0 wei5
35 - - - 06 OUTPUT 0 1 0 0 wei6
66 - - B -- OUTPUT 0 1 0 0 wei7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\zhangshuhua\szmb\miaobiao.rpt
miaobiao
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 17 OR2 ! 0 2 0 3 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:103
- 1 - B 17 OR2 ! 0 3 0 5 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:111
- 4 - B 19 AND2 0 2 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:115
- 6 - B 19 AND2 0 4 0 4 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:123
- 5 - B 16 AND2 0 3 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:131
- 1 - B 16 AND2 0 4 0 3 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:135
- 4 - B 13 AND2 0 3 0 3 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:143
- 7 - B 13 AND2 0 2 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|:147
- 8 - B 13 DFFE + 0 3 0 1 |CLKGEN:1|cnter14 (|CLKGEN:1|:3)
- 6 - B 13 DFFE + 0 3 0 2 |CLKGEN:1|cnter13 (|CLKGEN:1|:4)
- 5 - B 13 DFFE + 0 2 0 3 |CLKGEN:1|cnter12 (|CLKGEN:1|:5)
- 3 - B 13 DFFE + 0 3 0 2 |CLKGEN:1|cnter11 (|CLKGEN:1|:6)
- 1 - B 13 DFFE + 0 2 0 3 |CLKGEN:1|cnter10 (|CLKGEN:1|:7)
- 6 - B 16 DFFE + 0 2 0 2 |CLKGEN:1|cnter9 (|CLKGEN:1|:8)
- 4 - B 16 DFFE + 0 3 0 3 |CLKGEN:1|cnter8 (|CLKGEN:1|:9)
- 3 - B 16 DFFE + 0 2 0 4 |CLKGEN:1|cnter7 (|CLKGEN:1|:10)
- 7 - B 19 DFFE + 0 3 0 2 |CLKGEN:1|cnter6 (|CLKGEN:1|:11)
- 3 - B 19 DFFE + 0 3 0 3 |CLKGEN:1|cnter5 (|CLKGEN:1|:12)
- 2 - B 19 DFFE + 0 2 0 4 |CLKGEN:1|cnter4 (|CLKGEN:1|:13)
- 5 - B 17 DFFE + 0 3 0 1 |CLKGEN:1|cnter3 (|CLKGEN:1|:14)
- 6 - B 17 DFFE + 0 2 0 2 |CLKGEN:1|cnter2 (|CLKGEN:1|:15)
- 4 - B 17 DFFE + 0 2 0 1 |CLKGEN:1|cnter1 (|CLKGEN:1|:16)
- 2 - B 17 DFFE + 0 0 0 2 |CLKGEN:1|cnter0 (|CLKGEN:1|:17)
- 2 - B 16 OR2 s 0 4 0 1 |CLKGEN:1|~79~1
- 1 - B 19 OR2 s 0 3 0 1 |CLKGEN:1|~79~2
- 2 - B 13 OR2 s 0 4 0 1 |CLKGEN:1|~79~3
- 5 - B 19 OR2 ! 0 4 0 36 |CLKGEN:1|:79
- 8 - A 15 AND2 0 3 0 1 |CNT6:7|LPM_ADD_SUB:73|addcore:adder|:59
- 6 - A 15 OR2 0 3 0 1 |CNT6:7|LPM_ADD_SUB:73|addcore:adder|:68
- 7 - A 15 DFFE 1 3 1 3 |CNT6:7|cqi3 (|CNT6:7|:9)
- 4 - A 15 DFFE 1 3 1 5 |CNT6:7|cqi2 (|CNT6:7|:10)
- 1 - A 15 DFFE 1 3 1 5 |CNT6:7|cqi1 (|CNT6:7|:11)
- 2 - A 15 DFFE 1 1 1 6 |CNT6:7|cqi0 (|CNT6:7|:12)
- 3 - A 15 OR2 ! 0 4 0 3 |CNT6:7|:48
- 5 - A 15 AND2 0 4 0 4 |CNT6:7|:173
- 6 - A 19 AND2 0 3 0 1 |CNT6:8|LPM_ADD_SUB:73|addcore:adder|:59
- 5 - A 19 OR2 0 3 0 1 |CNT6:8|LPM_ADD_SUB:73|addcore:adder|:68
- 4 - A 19 DFFE 1 3 1 2 |CNT6:8|cqi3 (|CNT6:8|:9)
- 3 - A 19 DFFE 1 3 1 4 |CNT6:8|cqi2 (|CNT6:8|:10)
- 8 - A 19 DFFE 1 3 1 4 |CNT6:8|cqi1 (|CNT6:8|:11)
- 1 - A 19 DFFE 1 1 1 5 |CNT6:8|cqi0 (|CNT6:8|:12)
- 2 - A 19 OR2 ! 0 4 0 3 |CNT6:8|:48
- 3 - A 01 AND2 0 2 0 1 |CNT10:3|LPM_ADD_SUB:73|addcore:adder|:55
- 8 - A 01 OR2 0 4 0 1 |CNT10:3|LPM_ADD_SUB:73|addcore:adder|:69
- 6 - A 01 DFFE 1 3 1 4 |CNT10:3|cqi3 (|CNT10:3|:9)
- 7 - A 01 DFFE 1 3 1 4 |CNT10:3|cqi2 (|CNT10:3|:10)
- 5 - A 01 DFFE 1 3 1 5 |CNT10:3|cqi1 (|CNT10:3|:11)
- 1 - A 01 DFFE 1 1 1 6 |CNT10:3|cqi0 (|CNT10:3|:12)
- 2 - A 01 OR2 ! 0 4 0 3 |CNT10:3|:48
- 4 - A 01 AND2 0 4 0 4 |CNT10:3|:173
- 5 - A 11 AND2 0 2 0 1 |CNT10:4|LPM_ADD_SUB:73|addcore:adder|:55
- 6 - A 11 OR2 0 4 0 1 |CNT10:4|LPM_ADD_SUB:73|addcore:adder|:69
- 3 - A 11 DFFE 1 3 1 4 |CNT10:4|cqi3 (|CNT10:4|:9)
- 8 - A 11 DFFE 1 3 1 4 |CNT10:4|cqi2 (|CNT10:4|:10)
- 7 - A 11 DFFE 1 3 1 5 |CNT10:4|cqi1 (|CNT10:4|:11)
- 1 - A 11 DFFE 1 1 1 6 |CNT10:4|cqi0 (|CNT10:4|:12)
- 2 - A 11 OR2 ! 0 4 0 3 |CNT10:4|:48
- 4 - A 11 AND2 0 4 0 4 |CNT10:4|:173
- 6 - A 17 AND2 0 2 0 1 |CNT10:5|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - A 17 OR2 0 4 0 1 |CNT10:5|LPM_ADD_SUB:73|addcore:adder|:69
- 5 - A 17 DFFE 1 3 1 4 |CNT10:5|cqi3 (|CNT10:5|:9)
- 3 - A 17 DFFE 1 3 1 4 |CNT10:5|cqi2 (|CNT10:5|:10)
- 1 - A 17 DFFE 1 3 1 5 |CNT10:5|cqi1 (|CNT10:5|:11)
- 4 - A 17 DFFE 1 1 1 6 |CNT10:5|cqi0 (|CNT10:5|:12)
- 2 - A 17 OR2 ! 0 4 0 3 |CNT10:5|:48
- 8 - A 17 AND2 0 4 0 4 |CNT10:5|:173
- 6 - A 14 AND2 0 2 0 1 |CNT10:6|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - A 14 OR2 0 4 0 1 |CNT10:6|LPM_ADD_SUB:73|addcore:adder|:69
- 2 - A 14 DFFE 1 3 1 4 |CNT10:6|cqi3 (|CNT10:6|:9)
- 5 - A 14 DFFE 1 3 1 4 |CNT10:6|cqi2 (|CNT10:6|:10)
- 3 - A 14 DFFE 1 3 1 5 |CNT10:6|cqi1 (|CNT10:6|:11)
- 8 - A 14 DFFE 1 1 1 6 |CNT10:6|cqi0 (|CNT10:6|:12)
- 4 - A 14 OR2 ! 0 4 0 3 |CNT10:6|:48
- 1 - A 14 AND2 0 4 0 4 |CNT10:6|:173
- 2 - B 22 DFFE 0 4 1 0 |SAOS:9|:34
- 4 - A 05 DFFE 0 2 1 0 |SAOS:9|:36
- 8 - B 22 DFFE 0 4 1 0 |SAOS:9|:38
- 7 - B 22 DFFE 0 4 1 0 |SAOS:9|:40
- 1 - B 22 DFFE 0 4 1 0 |SAOS:9|:42
- 5 - B 22 DFFE 0 4 1 0 |SAOS:9|:44
- 6 - B 22 DFFE 0 4 1 0 |SAOS:9|:46
- 1 - A 23 DFFE 0 2 1 0 |SAOS:9|:48
- 8 - A 24 DFFE 0 5 1 0 |SAOS:9|:50
- 1 - A 21 DFFE 0 5 1 0 |SAOS:9|:52
- 4 - A 04 DFFE 0 4 1 0 |SAOS:9|:54
- 2 - A 21 DFFE 0 5 1 0 |SAOS:9|:56
- 6 - A 04 DFFE 0 4 1 0 |SAOS:9|:58
- 5 - A 04 DFFE 0 5 1 0 |SAOS:9|:60
- 1 - A 04 DFFE 0 5 1 0 |SAOS:9|:62
- 4 - B 22 DFFE 0 3 0 22 |SAOS:9|count2 (|SAOS:9|:66)
- 3 - B 22 DFFE 0 2 0 23 |SAOS:9|count1 (|SAOS:9|:67)
- 1 - B 24 DFFE 0 1 0 23 |SAOS:9|count0 (|SAOS:9|:68)
- 2 - A 23 AND2 0 3 0 5 |SAOS:9|:572
- 5 - A 20 OR2 ! 0 3 0 1 |SAOS:9|:584
- 1 - A 20 AND2 0 3 0 5 |SAOS:9|:596
- 5 - A 13 AND2 s 0 2 0 4 |SAOS:9|~687~1
- 3 - A 23 OR2 s 0 4 0 1 |SAOS:9|~709~1
- 4 - A 23 OR2 s ! 0 4 0 1 |SAOS:9|~709~2
- 5 - A 23 OR2 s 0 4 0 1 |SAOS:9|~709~3
- 6 - A 23 OR2 s ! 0 4 0 1 |SAOS:9|~709~4
- 7 - A 23 OR2 s 0 3 0 1 |SAOS:9|~709~5
- 8 - A 23 OR2 ! 0 4 0 14 |SAOS:9|:709
- 4 - A 20 OR2 ! 0 4 0 1 |SAOS:9|:722
- 2 - A 22 OR2 ! 0 4 0 1 |SAOS:9|:723
- 7 - A 20 OR2 ! 0 4 0 1 |SAOS:9|:724
- 3 - A 20 OR2 ! 0 4 0 1 |SAOS:9|:731
- 8 - A 20 OR2 ! 0 4 0 1 |SAOS:9|:732
- 2 - A 20 OR2 ! 0 4 0 14 |SAOS:9|:733
- 5 - A 22 OR2 s ! 0 4 0 1 |SAOS:9|~757~1
- 6 - A 22 OR2 s ! 0 4 0 1 |SAOS:9|~757~2
- 7 - A 22 OR2 s ! 0 4 0 1 |SAOS:9|~757~3
- 8 - A 22 OR2 s ! 0 3 0 1 |SAOS:9|~757~4
- 1 - A 13 AND2 s ! 0 4 0 1 |SAOS:9|~757~5
- 6 - A 13 OR2 0 4 0 14 |SAOS:9|:757
- 3 - A 22 OR2 s ! 0 4 0 1 |SAOS:9|~781~1
- 4 - A 22 OR2 s ! 0 4 0 1 |SAOS:9|~781~2
- 6 - A 20 OR2 s ! 0 4 0 1 |SAOS:9|~781~3
- 1 - A 22 OR2 s ! 0 3 0 1 |SAOS:9|~781~4
- 1 - A 24 AND2 s ! 0 4 0 1 |SAOS:9|~781~5
- 4 - A 24 OR2 0 4 0 12 |SAOS:9|:781
- 2 - A 24 AND2 s 0 2 0 1 |SAOS:9|~841~1
- 3 - A 24 OR2 ! 0 4 0 1 |SAOS:9|:877
- 5 - A 21 OR2 ! 0 4 0 2 |SAOS:9|:913
- 2 - A 04 OR2 ! 0 4 0 4 |SAOS:9|:949
- 8 - A 04 AND2 0 4 0 4 |SAOS:9|:961
- 6 - A 24 OR2 0 4 0 1 |SAOS:9|:991
- 7 - A 04 OR2 0 4 0 1 |SAOS:9|:1059
- 7 - A 24 OR2 0 4 0 1 |SAOS:9|:1083
- 5 - A 24 OR2 0 3 0 1 |SAOS:9|:1084
- 6 - A 21 OR2 0 4 0 1 |SAOS:9|:1101
- 3 - A 04 OR2 0 4 0 1 |SAOS:9|:1150
- 4 - A 21 OR2 s 0 4 0 2 |SAOS:9|~1192~1
- 3 - A 21 AND2 s 0 3 0 2 |SAOS:9|~1246~1
- 8 - A 21 OR2 s 0 2 0 1 |SAOS:9|~1246~2
- 7 - A 21 OR2 s ! 0 2 0 1 |SAOS:9|~1254~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\zhangshuhua\szmb\miaobiao.rpt
miaobiao
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 21/ 96( 21%) 4/ 48( 8%) 35/ 48( 72%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 11/ 48( 22%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zhangshuhua\szmb\miaobiao.rpt
miaobiao
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 36 |CLKGEN:1|:79
INPUT 15 clk
LCELL 4 |CNT6:7|:173
LCELL 4 |CNT10:3|:173
LCELL 4 |CNT10:4|:173
LCELL 4 |CNT10:5|:173
LCELL 4 |CNT10:6|:173
Device-Specific Information: d:\zhangshuhua\szmb\miaobiao.rpt
miaobiao
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 clr
Device-Specific Information: d:\zhangshuhua\szmb\miaobiao.rpt
miaobiao
** EQUATIONS **
clk : INPUT;
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