📄 cnt6.rpt
字号:
- 6 - A 01 OR2 0 3 0 1 |LPM_ADD_SUB:73|addcore:adder|:68
- 7 - A 01 DFFE + 1 2 1 2 cqi3 (:9)
- 2 - A 01 DFFE + 1 2 1 4 cqi2 (:10)
- 5 - A 01 DFFE + 1 2 1 4 cqi1 (:11)
- 1 - A 01 DFFE + 1 0 1 5 cqi0 (:12)
- 4 - A 01 OR2 ! 0 4 0 3 :48
- 3 - A 01 AND2 0 4 1 0 :173
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zhangshuhua\szmb\cnt6.rpt
cnt6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zhangshuhua\szmb\cnt6.rpt
cnt6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: f:\zhangshuhua\szmb\cnt6.rpt
cnt6
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: f:\zhangshuhua\szmb\cnt6.rpt
cnt6
** EQUATIONS **
clk : INPUT;
clr : INPUT;
ena : INPUT;
-- Node name is 'carry_out'
-- Equation name is 'carry_out', type is output
carry_out = _LC3_A1;
-- Node name is ':12' = 'cqi0'
-- Equation name is 'cqi0', location is LC1_A1, type is buried.
cqi0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = cqi0 & !ena
# !cqi0 & ena;
-- Node name is ':11' = 'cqi1'
-- Equation name is 'cqi1', location is LC5_A1, type is buried.
cqi1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !cqi0 & cqi1 & !_LC4_A1
# cqi0 & !cqi1 & ena & !_LC4_A1
# cqi1 & !ena;
-- Node name is ':10' = 'cqi2'
-- Equation name is 'cqi2', location is LC2_A1, type is buried.
cqi2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = ena & !_LC4_A1 & _LC6_A1
# cqi2 & !ena;
-- Node name is ':9' = 'cqi3'
-- Equation name is 'cqi3', location is LC7_A1, type is buried.
cqi3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = cqi3 & !_LC4_A1 & !_LC8_A1
# !cqi3 & ena & !_LC4_A1 & _LC8_A1
# cqi3 & !ena;
-- Node name is 'cq0'
-- Equation name is 'cq0', type is output
cq0 = cqi0;
-- Node name is 'cq1'
-- Equation name is 'cq1', type is output
cq1 = cqi1;
-- Node name is 'cq2'
-- Equation name is 'cq2', type is output
cq2 = cqi2;
-- Node name is 'cq3'
-- Equation name is 'cq3', type is output
cq3 = cqi3;
-- Node name is '|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ005);
_EQ005 = cqi0 & cqi1 & cqi2;
-- Node name is '|LPM_ADD_SUB:73|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ006);
_EQ006 = !cqi1 & cqi2
# !cqi0 & cqi2
# cqi0 & cqi1 & !cqi2;
-- Node name is ':48'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ007);
_EQ007 = !cqi2
# cqi3
# cqi1
# !cqi0;
-- Node name is ':173'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ008);
_EQ008 = !cqi0 & !cqi1 & !cqi2 & !cqi3;
Project Information f:\zhangshuhua\szmb\cnt6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,371K
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