📄 times.rpt
字号:
66 - - B -- OUTPUT 0 1 0 0 dout14
67 - - B -- OUTPUT 0 1 0 0 dout15
58 - - C -- OUTPUT 0 1 0 0 dout16
61 - - C -- OUTPUT 0 1 0 0 dout17
60 - - C -- OUTPUT 0 1 0 0 dout18
59 - - C -- OUTPUT 0 1 0 0 dout19
22 - - B -- OUTPUT 0 1 0 0 dout20
21 - - B -- OUTPUT 0 1 0 0 dout21
25 - - B -- OUTPUT 0 1 0 0 dout22
24 - - B -- OUTPUT 0 1 0 0 dout23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zhangshuhua\szmb\times.rpt
times
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 16 OR2 ! 0 2 0 3 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:103
- 1 - A 16 OR2 ! 0 3 0 5 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:111
- 5 - A 20 AND2 0 2 0 1 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:115
- 8 - A 20 AND2 0 4 0 4 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:123
- 5 - A 14 AND2 0 3 0 1 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:131
- 1 - A 14 AND2 0 4 0 3 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:135
- 4 - A 21 AND2 0 3 0 3 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:143
- 7 - A 21 AND2 0 2 0 1 |clkgen:u0|LPM_ADD_SUB:188|addcore:adder|:147
- 8 - A 21 DFFE + 0 3 0 1 |clkgen:u0|cnter14 (|clkgen:u0|:3)
- 6 - A 21 DFFE + 0 3 0 2 |clkgen:u0|cnter13 (|clkgen:u0|:4)
- 5 - A 21 DFFE + 0 2 0 3 |clkgen:u0|cnter12 (|clkgen:u0|:5)
- 3 - A 21 DFFE + 0 3 0 2 |clkgen:u0|cnter11 (|clkgen:u0|:6)
- 1 - A 21 DFFE + 0 2 0 3 |clkgen:u0|cnter10 (|clkgen:u0|:7)
- 6 - A 14 DFFE + 0 2 0 2 |clkgen:u0|cnter9 (|clkgen:u0|:8)
- 4 - A 14 DFFE + 0 3 0 3 |clkgen:u0|cnter8 (|clkgen:u0|:9)
- 3 - A 14 DFFE + 0 2 0 4 |clkgen:u0|cnter7 (|clkgen:u0|:10)
- 6 - A 20 DFFE + 0 3 0 2 |clkgen:u0|cnter6 (|clkgen:u0|:11)
- 4 - A 20 DFFE + 0 3 0 3 |clkgen:u0|cnter5 (|clkgen:u0|:12)
- 3 - A 20 DFFE + 0 2 0 4 |clkgen:u0|cnter4 (|clkgen:u0|:13)
- 5 - A 16 DFFE + 0 3 0 1 |clkgen:u0|cnter3 (|clkgen:u0|:14)
- 6 - A 16 DFFE + 0 2 0 2 |clkgen:u0|cnter2 (|clkgen:u0|:15)
- 4 - A 16 DFFE + 0 2 0 1 |clkgen:u0|cnter1 (|clkgen:u0|:16)
- 2 - A 16 DFFE + 0 0 0 2 |clkgen:u0|cnter0 (|clkgen:u0|:17)
- 2 - A 14 OR2 s 0 4 0 1 |clkgen:u0|~79~1
- 2 - A 20 OR2 s 0 3 0 1 |clkgen:u0|~79~2
- 2 - A 21 OR2 s 0 4 0 1 |clkgen:u0|~79~3
- 1 - A 20 OR2 ! 0 4 0 18 |clkgen:u0|:79
- 7 - B 16 AND2 0 3 0 1 |cnt6:u4|LPM_ADD_SUB:73|addcore:adder|:59
- 6 - B 16 OR2 0 3 0 1 |cnt6:u4|LPM_ADD_SUB:73|addcore:adder|:68
- 1 - B 16 DFFE 1 3 1 2 |cnt6:u4|cqi3 (|cnt6:u4|:9)
- 2 - B 16 DFFE 1 3 1 4 |cnt6:u4|cqi2 (|cnt6:u4|:10)
- 5 - B 16 DFFE 1 3 1 4 |cnt6:u4|cqi1 (|cnt6:u4|:11)
- 7 - B 03 DFFE 1 1 1 5 |cnt6:u4|cqi0 (|cnt6:u4|:12)
- 4 - B 16 OR2 ! 0 4 0 3 |cnt6:u4|:48
- 3 - B 16 AND2 0 4 0 4 |cnt6:u4|:173
- 5 - B 03 AND2 0 3 0 1 |cnt6:u6|LPM_ADD_SUB:73|addcore:adder|:59
- 4 - B 03 OR2 0 3 0 1 |cnt6:u6|LPM_ADD_SUB:73|addcore:adder|:68
- 6 - B 03 DFFE 1 3 1 1 |cnt6:u6|cqi3 (|cnt6:u6|:9)
- 8 - B 03 DFFE 1 3 1 3 |cnt6:u6|cqi2 (|cnt6:u6|:10)
- 1 - B 03 DFFE 1 3 1 3 |cnt6:u6|cqi1 (|cnt6:u6|:11)
- 2 - B 03 DFFE 1 1 1 4 |cnt6:u6|cqi0 (|cnt6:u6|:12)
- 3 - B 03 OR2 ! 0 4 0 3 |cnt6:u6|:48
- 6 - A 09 AND2 0 2 0 1 |cnt10:u1|LPM_ADD_SUB:73|addcore:adder|:55
- 8 - A 09 OR2 0 4 0 1 |cnt10:u1|LPM_ADD_SUB:73|addcore:adder|:69
- 3 - A 09 DFFE 1 3 1 3 |cnt10:u1|cqi3 (|cnt10:u1|:9)
- 5 - A 09 DFFE 1 3 1 3 |cnt10:u1|cqi2 (|cnt10:u1|:10)
- 7 - A 09 DFFE 1 3 1 4 |cnt10:u1|cqi1 (|cnt10:u1|:11)
- 1 - A 09 DFFE 1 1 1 5 |cnt10:u1|cqi0 (|cnt10:u1|:12)
- 4 - A 09 OR2 ! 0 4 0 3 |cnt10:u1|:48
- 2 - A 09 AND2 0 4 0 4 |cnt10:u1|:173
- 5 - A 18 AND2 0 2 0 1 |cnt10:u2|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - A 18 OR2 0 4 0 1 |cnt10:u2|LPM_ADD_SUB:73|addcore:adder|:69
- 8 - A 18 DFFE 1 3 1 3 |cnt10:u2|cqi3 (|cnt10:u2|:9)
- 4 - A 18 DFFE 1 3 1 3 |cnt10:u2|cqi2 (|cnt10:u2|:10)
- 3 - A 18 DFFE 1 3 1 4 |cnt10:u2|cqi1 (|cnt10:u2|:11)
- 1 - A 18 DFFE 1 1 1 5 |cnt10:u2|cqi0 (|cnt10:u2|:12)
- 2 - A 18 OR2 ! 0 4 0 3 |cnt10:u2|:48
- 6 - A 18 AND2 0 4 0 4 |cnt10:u2|:173
- 7 - C 02 AND2 0 2 0 1 |cnt10:u3|LPM_ADD_SUB:73|addcore:adder|:55
- 8 - C 02 OR2 0 4 0 1 |cnt10:u3|LPM_ADD_SUB:73|addcore:adder|:69
- 5 - C 02 DFFE 1 3 1 3 |cnt10:u3|cqi3 (|cnt10:u3|:9)
- 1 - C 02 DFFE 1 3 1 3 |cnt10:u3|cqi2 (|cnt10:u3|:10)
- 6 - C 02 DFFE 1 3 1 4 |cnt10:u3|cqi1 (|cnt10:u3|:11)
- 2 - C 02 DFFE 1 1 1 5 |cnt10:u3|cqi0 (|cnt10:u3|:12)
- 4 - C 02 OR2 ! 0 4 0 3 |cnt10:u3|:48
- 3 - C 02 AND2 0 4 0 4 |cnt10:u3|:173
- 6 - C 16 AND2 0 2 0 1 |cnt10:u5|LPM_ADD_SUB:73|addcore:adder|:55
- 8 - C 16 OR2 0 4 0 1 |cnt10:u5|LPM_ADD_SUB:73|addcore:adder|:69
- 5 - C 16 DFFE 1 3 1 3 |cnt10:u5|cqi3 (|cnt10:u5|:9)
- 3 - C 16 DFFE 1 3 1 3 |cnt10:u5|cqi2 (|cnt10:u5|:10)
- 2 - C 16 DFFE 1 3 1 4 |cnt10:u5|cqi1 (|cnt10:u5|:11)
- 7 - C 16 DFFE 1 1 1 5 |cnt10:u5|cqi0 (|cnt10:u5|:12)
- 4 - C 16 OR2 ! 0 4 0 3 |cnt10:u5|:48
- 1 - C 16 AND2 0 4 0 4 |cnt10:u5|:173
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zhangshuhua\szmb\times.rpt
times
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 3/ 48( 6%) 10/ 48( 20%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 5/ 96( 5%) 2/ 48( 4%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 2/ 96( 2%) 4/ 48( 8%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zhangshuhua\szmb\times.rpt
times
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 18 |clkgen:u0|:79
INPUT 15 clk
LCELL 4 |cnt6:u4|:173
LCELL 4 |cnt10:u1|:173
LCELL 4 |cnt10:u2|:173
LCELL 4 |cnt10:u3|:173
LCELL 4 |cnt10:u5|:173
Device-Specific Information: f:\zhangshuhua\szmb\times.rpt
times
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 clr
Device-Specific Information: f:\zhangshuhua\szmb\times.rpt
times
** EQUATIONS **
clk : INPUT;
clr : INPUT;
ena : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC1_A9;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC7_A9;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC5_A9;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC3_A9;
-- Node name is 'dout4'
-- Equation name is 'dout4', type is output
dout4 = _LC1_A18;
-- Node name is 'dout5'
-- Equation name is 'dout5', type is output
dout5 = _LC3_A18;
-- Node name is 'dout6'
-- Equation name is 'dout6', type is output
dout6 = _LC4_A18;
-- Node name is 'dout7'
-- Equation name is 'dout7', type is output
dout7 = _LC8_A18;
-- Node name is 'dout8'
-- Equation name is 'dout8', type is output
dout8 = _LC2_C2;
-- Node name is 'dout9'
-- Equation name is 'dout9', type is output
dout9 = _LC6_C2;
-- Node name is 'dout10'
-- Equation name is 'dout10', type is output
dout10 = _LC1_C2;
-- Node name is 'dout11'
-- Equation name is 'dout11', type is output
dout11 = _LC5_C2;
-- Node name is 'dout12'
-- Equation name is 'dout12', type is output
dout12 = _LC7_B3;
-- Node name is 'dout13'
-- Equation name is 'dout13', type is output
dout13 = _LC5_B16;
-- Node name is 'dout14'
-- Equation name is 'dout14', type is output
dout14 = _LC2_B16;
-- Node name is 'dout15'
-- Equation name is 'dout15', type is output
dout15 = _LC1_B16;
-- Node name is 'dout16'
-- Equation name is 'dout16', type is output
dout16 = _LC7_C16;
-- Node name is 'dout17'
-- Equation name is 'dout17', type is output
dout17 = _LC2_C16;
-- Node name is 'dout18'
-- Equation name is 'dout18', type is output
dout18 = _LC3_C16;
-- Node name is 'dout19'
-- Equation name is 'dout19', type is output
dout19 = _LC5_C16;
-- Node name is 'dout20'
-- Equation name is 'dout20', type is output
dout20 = _LC2_B3;
-- Node name is 'dout21'
-- Equation name is 'dout21', type is output
dout21 = _LC1_B3;
-- Node name is 'dout22'
-- Equation name is 'dout22', type is output
dout22 = _LC8_B3;
-- Node name is 'dout23'
-- Equation name is 'dout23', type is output
dout23 = _LC6_B3;
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