📄 shuzimiaobiao.rpt
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# !_LC6_C14;
-- Node name is '|SAOS:9|:733'
-- Equation name is '_LC8_C14', type is buried
!_LC8_C14 = _LC8_C14~NOT;
_LC8_C14~NOT = LCELL( _EQ087);
_EQ087 = !_LC1_C24 & !_LC2_C14 & !_LC7_C14
# !_LC1_C13 & !_LC2_C14 & !_LC7_C14
# !_LC1_C13 & _LC1_C24;
-- Node name is '|SAOS:9|~757~1'
-- Equation name is '_LC4_C24', type is buried
-- synthesized logic cell
!_LC4_C24 = _LC4_C24~NOT;
_LC4_C24~NOT = LCELL( _EQ088);
_EQ088 = _LC2_C12 & _LC6_C15 & !_LC7_C12
# !_LC2_C12 & _LC4_C23 & !_LC6_C15 & _LC7_C12;
-- Node name is '|SAOS:9|~757~2'
-- Equation name is '_LC6_C24', type is buried
-- synthesized logic cell
!_LC6_C24 = _LC6_C24~NOT;
_LC6_C24~NOT = LCELL( _EQ089);
_EQ089 = !_LC2_C12 & !_LC6_C15
# _LC7_C12
# _LC2_C12 & _LC2_C21 & _LC6_C15;
-- Node name is '|SAOS:9|~757~3'
-- Equation name is '_LC5_C18', type is buried
-- synthesized logic cell
!_LC5_C18 = _LC5_C18~NOT;
_LC5_C18~NOT = LCELL( _EQ090);
_EQ090 = _LC2_C15 & _LC4_C12 & _LC7_C19
# _LC2_C15 & !_LC4_C12 & _LC4_C17
# _LC2_C15 & _LC4_C17 & _LC7_C19;
-- Node name is '|SAOS:9|~757~4'
-- Equation name is '_LC7_C24', type is buried
-- synthesized logic cell
!_LC7_C24 = _LC7_C24~NOT;
_LC7_C24~NOT = LCELL( _EQ091);
_EQ091 = !_LC4_C24 & !_LC6_C24
# !_LC5_C18 & !_LC6_C24;
-- Node name is '|SAOS:9|~757~5'
-- Equation name is '_LC8_C24', type is buried
-- synthesized logic cell
!_LC8_C24 = _LC8_C24~NOT;
_LC8_C24~NOT = LCELL( _EQ092);
_EQ092 = !_LC2_C12 & _LC4_C22 & _LC6_C15 & !_LC7_C12;
-- Node name is '|SAOS:9|:757'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = LCELL( _EQ093);
_EQ093 = !_LC1_C24 & !_LC7_C24
# !_LC1_C24 & !_LC8_C24
# _LC3_C13 & !_LC7_C24
# _LC3_C13 & !_LC8_C24
# _LC1_C24 & _LC3_C13;
-- Node name is '|SAOS:9|~781~1'
-- Equation name is '_LC1_C18', type is buried
-- synthesized logic cell
!_LC1_C18 = _LC1_C18~NOT;
_LC1_C18~NOT = LCELL( _EQ094);
_EQ094 = _LC2_C12 & _LC6_C15 & !_LC7_C12
# _LC1_C23 & !_LC2_C12 & !_LC6_C15 & _LC7_C12;
-- Node name is '|SAOS:9|~781~2'
-- Equation name is '_LC4_C18', type is buried
-- synthesized logic cell
!_LC4_C18 = _LC4_C18~NOT;
_LC4_C18~NOT = LCELL( _EQ095);
_EQ095 = !_LC2_C12 & !_LC6_C15
# _LC7_C12
# _LC2_C12 & _LC5_C21 & _LC6_C15;
-- Node name is '|SAOS:9|~781~3'
-- Equation name is '_LC6_C18', type is buried
-- synthesized logic cell
!_LC6_C18 = _LC6_C18~NOT;
_LC6_C18~NOT = LCELL( _EQ096);
_EQ096 = _LC2_C15 & _LC2_C19 & _LC4_C12
# _LC2_C15 & !_LC4_C12 & _LC6_C17
# _LC2_C15 & _LC2_C19 & _LC6_C17;
-- Node name is '|SAOS:9|~781~4'
-- Equation name is '_LC7_C18', type is buried
-- synthesized logic cell
!_LC7_C18 = _LC7_C18~NOT;
_LC7_C18~NOT = LCELL( _EQ097);
_EQ097 = !_LC1_C18 & !_LC4_C18
# !_LC4_C18 & !_LC6_C18;
-- Node name is '|SAOS:9|~781~5'
-- Equation name is '_LC8_C18', type is buried
-- synthesized logic cell
!_LC8_C18 = _LC8_C18~NOT;
_LC8_C18~NOT = LCELL( _EQ098);
_EQ098 = !_LC2_C12 & _LC5_C22 & _LC6_C15 & !_LC7_C12;
-- Node name is '|SAOS:9|:781'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = LCELL( _EQ099);
_EQ099 = !_LC1_C24 & !_LC7_C18
# !_LC1_C24 & !_LC8_C18
# _LC4_C13 & !_LC7_C18
# _LC4_C13 & !_LC8_C18
# _LC1_C24 & _LC4_C13;
-- Node name is '|SAOS:9|~841~1'
-- Equation name is '_LC6_C3', type is buried
-- synthesized logic cell
_LC6_C3 = LCELL( _EQ100);
_EQ100 = _LC1_C15 & !_LC8_C14;
-- Node name is '|SAOS:9|:877'
-- Equation name is '_LC6_C8', type is buried
!_LC6_C8 = _LC6_C8~NOT;
_LC6_C8~NOT = LCELL( _EQ101);
_EQ101 = !_LC3_C24
# !_LC2_C18
# _LC1_C15
# !_LC8_C14;
-- Node name is '|SAOS:9|:913'
-- Equation name is '_LC4_C8', type is buried
!_LC4_C8 = _LC4_C8~NOT;
_LC4_C8~NOT = LCELL( _EQ102);
_EQ102 = _LC3_C24
# _LC2_C18
# _LC1_C15
# !_LC8_C14;
-- Node name is '|SAOS:9|:949'
-- Equation name is '_LC2_C8', type is buried
!_LC2_C8 = _LC2_C8~NOT;
_LC2_C8~NOT = LCELL( _EQ103);
_EQ103 = _LC3_C24
# !_LC2_C18
# _LC1_C15
# _LC8_C14;
-- Node name is '|SAOS:9|:961'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = LCELL( _EQ104);
_EQ104 = !_LC1_C15 & !_LC2_C18 & !_LC3_C24 & !_LC8_C14;
-- Node name is '|SAOS:9|:991'
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ105);
_EQ105 = _LC1_C15 & !_LC2_C18 & !_LC8_C14
# _LC1_C15 & !_LC3_C24 & !_LC8_C14
# !_LC1_C15 & _LC2_C18 & _LC3_C24 & _LC8_C14
# _LC1_C15 & _LC2_C18 & !_LC3_C24;
-- Node name is '|SAOS:9|:1059'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ106);
_EQ106 = _LC1_C15 & !_LC8_C14
# _LC1_C15 & _LC2_C18 & !_LC3_C24
# !_LC1_C15 & _LC8_C14
# !_LC1_C15 & _LC2_C18 & _LC3_C24;
-- Node name is '|SAOS:9|:1083'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = LCELL( _EQ107);
_EQ107 = _LC1_C15 & _LC2_C18 & _LC3_C24 & !_LC8_C14
# _LC1_C15 & !_LC2_C18 & _LC8_C14
# _LC1_C15 & !_LC3_C24 & _LC8_C14;
-- Node name is '|SAOS:9|:1084'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( _EQ108);
_EQ108 = !_LC3_C24 & _LC6_C3
# _LC7_C3;
-- Node name is '|SAOS:9|:1101'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ109);
_EQ109 = !_LC4_C8 & _LC5_C8
# _LC1_C3 & !_LC4_C8 & !_LC6_C8;
-- Node name is '|SAOS:9|:1150'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = LCELL( _EQ110);
_EQ110 = !_LC2_C18 & _LC3_C24
# !_LC2_C18 & !_LC8_C14
# _LC1_C15 & _LC8_C14
# _LC1_C15 & _LC3_C24
# _LC1_C15 & !_LC2_C18
# !_LC1_C15 & !_LC3_C24 & !_LC8_C14;
-- Node name is '|SAOS:9|~1192~1'
-- Equation name is '_LC5_C8', type is buried
-- synthesized logic cell
_LC5_C8 = LCELL( _EQ111);
_EQ111 = !_LC1_C15 & !_LC2_C18 & _LC3_C24 & _LC8_C14
# !_LC1_C15 & _LC2_C18 & !_LC3_C24 & _LC8_C14;
-- Node name is '|SAOS:9|~1246~1'
-- Equation name is '_LC3_C2', type is buried
-- synthesized logic cell
_LC3_C2 = LCELL( _EQ112);
_EQ112 = !_LC1_C15 & _LC3_C24 & !_LC8_C14;
-- Node name is '|SAOS:9|~1246~2'
-- Equation name is '_LC7_C2', type is buried
-- synthesized logic cell
_LC7_C2 = LCELL( _EQ113);
_EQ113 = _LC3_C2
# _LC4_C8;
-- Node name is '|SAOS:9|~1254~1'
-- Equation name is '_LC6_C2', type is buried
-- synthesized logic cell
!_LC6_C2 = _LC6_C2~NOT;
_LC6_C2~NOT = LCELL( _EQ114);
_EQ114 = _LC8_C8
# _LC2_C8;
Project Information d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time
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