📄 shuzimiaobiao.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
shuzimiaobiao
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
5 - - - 05 OUTPUT 0 0 0 0 duan0
6 - - - 04 OUTPUT 0 1 0 0 duan1
7 - - - 03 OUTPUT 0 1 0 0 duan2
8 - - - 03 OUTPUT 0 1 0 0 duan3
9 - - - 02 OUTPUT 0 1 0 0 duan4
10 - - - 01 OUTPUT 0 1 0 0 duan5
11 - - - 01 OUTPUT 0 1 0 0 duan6
16 - - A -- OUTPUT 0 1 0 0 duan7
72 - - A -- OUTPUT 0 1 0 0 wei0
73 - - A -- OUTPUT 0 1 0 0 wei1
78 - - - 24 OUTPUT 0 0 0 0 wei2
79 - - - 24 OUTPUT 0 1 0 0 wei3
80 - - - 23 OUTPUT 0 1 0 0 wei4
81 - - - 22 OUTPUT 0 0 0 0 wei5
83 - - - 13 OUTPUT 0 1 0 0 wei6
3 - - - 12 OUTPUT 0 1 0 0 wei7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
shuzimiaobiao
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 19 AND2 0 3 0 3 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|:71
- 2 - B 20 AND2 0 2 0 1 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|:75
- 5 - B 19 DFFE + 0 3 0 1 |CLKGEN:1|cnter5 (|CLKGEN:1|:3)
- 4 - B 19 DFFE + 0 3 0 2 |CLKGEN:1|cnter4 (|CLKGEN:1|:4)
- 1 - B 20 DFFE + 0 2 0 3 |CLKGEN:1|cnter3 (|CLKGEN:1|:5)
- 8 - B 19 DFFE + 0 2 0 3 |CLKGEN:1|cnter2 (|CLKGEN:1|:6)
- 7 - B 19 DFFE + 0 1 0 4 |CLKGEN:1|cnter1 (|CLKGEN:1|:7)
- 6 - B 19 DFFE + 0 3 0 4 |CLKGEN:1|cnter0 (|CLKGEN:1|:8)
- 3 - B 19 OR2 s 0 3 0 2 |CLKGEN:1|~34~1
- 2 - B 19 OR2 ! 0 4 0 7 |CLKGEN:1|:34
- 1 - C 17 AND2 0 2 0 1 |CNT6:8|LPM_ADD_SUB:73|addcore:adder|:55
- 8 - C 17 AND2 0 3 0 1 |CNT6:8|LPM_ADD_SUB:73|addcore:adder|:59
- 7 - C 17 DFFE 2 3 0 2 |CNT6:8|cqi3 (|CNT6:8|:9)
- 5 - C 17 DFFE 2 3 0 3 |CNT6:8|cqi2 (|CNT6:8|:10)
- 4 - C 17 DFFE 2 3 0 4 |CNT6:8|cqi1 (|CNT6:8|:11)
- 6 - C 17 DFFE 2 1 0 5 |CNT6:8|cqi0 (|CNT6:8|:12)
- 2 - C 17 OR2 s 0 3 0 2 |CNT6:8|~48~1
- 3 - C 17 OR2 s 1 2 0 2 |CNT6:8|~138~1
- 5 - C 23 AND2 0 2 0 1 |CNT6:18|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - C 23 AND2 0 3 0 1 |CNT6:18|LPM_ADD_SUB:73|addcore:adder|:59
- 8 - C 23 DFFE 2 3 0 3 |CNT6:18|cqi3 (|CNT6:18|:9)
- 3 - C 23 DFFE 2 3 0 4 |CNT6:18|cqi2 (|CNT6:18|:10)
- 4 - C 23 DFFE 2 3 0 5 |CNT6:18|cqi1 (|CNT6:18|:11)
- 1 - C 23 DFFE 2 1 0 6 |CNT6:18|cqi0 (|CNT6:18|:12)
- 6 - C 23 OR2 ! 0 4 0 3 |CNT6:18|:48
- 2 - C 23 AND2 0 4 0 4 |CNT6:18|:173
- 6 - C 13 AND2 0 2 0 1 |CNT10:3|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - C 13 AND2 0 3 0 1 |CNT10:3|LPM_ADD_SUB:73|addcore:adder|:59
- 5 - C 13 DFFE 2 3 0 3 |CNT10:3|cqi3 (|CNT10:3|:9)
- 1 - C 13 DFFE 2 3 0 4 |CNT10:3|cqi2 (|CNT10:3|:10)
- 3 - C 13 DFFE 2 3 0 5 |CNT10:3|cqi1 (|CNT10:3|:11)
- 4 - C 13 DFFE 2 1 0 6 |CNT10:3|cqi0 (|CNT10:3|:12)
- 2 - C 13 OR2 ! 0 4 0 3 |CNT10:3|:48
- 8 - C 13 AND2 0 4 0 4 |CNT10:3|:173
- 2 - C 22 AND2 0 2 0 1 |CNT10:4|LPM_ADD_SUB:73|addcore:adder|:55
- 6 - C 22 AND2 0 3 0 1 |CNT10:4|LPM_ADD_SUB:73|addcore:adder|:59
- 7 - C 22 DFFE 2 3 0 3 |CNT10:4|cqi3 (|CNT10:4|:9)
- 8 - C 22 DFFE 2 3 0 4 |CNT10:4|cqi2 (|CNT10:4|:10)
- 4 - C 22 DFFE 2 3 0 5 |CNT10:4|cqi1 (|CNT10:4|:11)
- 5 - C 22 DFFE 2 1 0 6 |CNT10:4|cqi0 (|CNT10:4|:12)
- 3 - C 22 OR2 ! 0 4 0 3 |CNT10:4|:48
- 1 - C 22 AND2 0 4 0 4 |CNT10:4|:173
- 3 - C 21 AND2 0 2 0 1 |CNT10:5|LPM_ADD_SUB:73|addcore:adder|:55
- 7 - C 21 AND2 0 3 0 1 |CNT10:5|LPM_ADD_SUB:73|addcore:adder|:59
- 8 - C 21 DFFE 2 3 0 3 |CNT10:5|cqi3 (|CNT10:5|:9)
- 6 - C 21 DFFE 2 3 0 4 |CNT10:5|cqi2 (|CNT10:5|:10)
- 2 - C 21 DFFE 2 3 0 5 |CNT10:5|cqi1 (|CNT10:5|:11)
- 5 - C 21 DFFE 2 1 0 6 |CNT10:5|cqi0 (|CNT10:5|:12)
- 1 - C 21 OR2 ! 0 4 0 3 |CNT10:5|:48
- 4 - C 21 AND2 0 4 0 4 |CNT10:5|:173
- 3 - C 19 AND2 0 2 0 1 |CNT10:19|LPM_ADD_SUB:73|addcore:adder|:55
- 8 - C 19 AND2 0 3 0 1 |CNT10:19|LPM_ADD_SUB:73|addcore:adder|:59
- 5 - C 19 DFFE 2 3 0 3 |CNT10:19|cqi3 (|CNT10:19|:9)
- 6 - C 19 DFFE 2 3 0 4 |CNT10:19|cqi2 (|CNT10:19|:10)
- 7 - C 19 DFFE 2 3 0 5 |CNT10:19|cqi1 (|CNT10:19|:11)
- 2 - C 19 DFFE 2 1 0 6 |CNT10:19|cqi0 (|CNT10:19|:12)
- 4 - C 19 OR2 ! 0 4 0 3 |CNT10:19|:48
- 1 - C 19 AND2 0 4 0 4 |CNT10:19|:173
- 5 - C 12 DFFE + 0 3 1 0 |SAOS:9|:34
- 1 - C 14 DFFE + 0 1 1 0 |SAOS:9|:36
- 5 - C 24 DFFE + 0 3 1 0 |SAOS:9|:40
- 2 - C 24 DFFE + 0 3 1 0 |SAOS:9|:42
- 1 - C 12 DFFE + 0 3 1 0 |SAOS:9|:46
- 3 - C 15 DFFE + 0 1 1 0 |SAOS:9|:48
- 1 - C 08 DFFE + 0 4 1 0 |SAOS:9|:50
- 2 - C 02 DFFE + 0 4 1 0 |SAOS:9|:52
- 4 - C 02 DFFE + 0 3 1 0 |SAOS:9|:54
- 1 - C 02 DFFE + 0 4 1 0 |SAOS:9|:56
- 2 - C 03 DFFE + 0 3 1 0 |SAOS:9|:58
- 3 - C 03 DFFE + 0 4 1 0 |SAOS:9|:60
- 4 - C 03 DFFE + 0 4 1 0 |SAOS:9|:62
- 7 - C 12 DFFE + 0 2 0 20 |SAOS:9|count2 (|SAOS:9|:66)
- 2 - C 12 DFFE + 0 1 0 21 |SAOS:9|count1 (|SAOS:9|:67)
- 6 - C 15 DFFE + 0 0 0 21 |SAOS:9|count0 (|SAOS:9|:68)
- 2 - C 15 AND2 s ! 0 2 0 4 |SAOS:9|~396~1
- 1 - C 24 AND2 0 3 0 5 |SAOS:9|:572
- 3 - C 14 AND2 0 3 0 1 |SAOS:9|:584
- 4 - C 12 AND2 0 3 0 5 |SAOS:9|:596
- 4 - C 15 OR2 s 0 4 0 1 |SAOS:9|~709~1
- 3 - C 12 OR2 s ! 0 4 0 1 |SAOS:9|~709~2
- 3 - C 18 OR2 s 0 4 0 1 |SAOS:9|~709~3
- 6 - C 12 OR2 s ! 0 4 0 1 |SAOS:9|~709~4
- 8 - C 12 OR2 s 0 3 0 1 |SAOS:9|~709~5
- 1 - C 15 OR2 ! 0 4 0 14 |SAOS:9|:709
- 5 - C 14 OR2 ! 0 4 0 1 |SAOS:9|:722
- 4 - C 14 OR2 ! 0 4 0 1 |SAOS:9|:723
- 6 - C 14 OR2 ! 0 4 0 1 |SAOS:9|:724
- 2 - C 14 OR2 ! 0 4 0 1 |SAOS:9|:731
- 7 - C 14 OR2 ! 0 4 0 1 |SAOS:9|:732
- 8 - C 14 OR2 ! 0 4 0 14 |SAOS:9|:733
- 4 - C 24 OR2 s ! 0 4 0 1 |SAOS:9|~757~1
- 6 - C 24 OR2 s ! 0 4 0 1 |SAOS:9|~757~2
- 5 - C 18 OR2 s ! 0 4 0 1 |SAOS:9|~757~3
- 7 - C 24 OR2 s ! 0 3 0 1 |SAOS:9|~757~4
- 8 - C 24 AND2 s ! 0 4 0 1 |SAOS:9|~757~5
- 3 - C 24 OR2 0 4 0 14 |SAOS:9|:757
- 1 - C 18 OR2 s ! 0 4 0 1 |SAOS:9|~781~1
- 4 - C 18 OR2 s ! 0 4 0 1 |SAOS:9|~781~2
- 6 - C 18 OR2 s ! 0 4 0 1 |SAOS:9|~781~3
- 7 - C 18 OR2 s ! 0 3 0 1 |SAOS:9|~781~4
- 8 - C 18 AND2 s ! 0 4 0 1 |SAOS:9|~781~5
- 2 - C 18 OR2 0 4 0 12 |SAOS:9|:781
- 6 - C 03 AND2 s 0 2 0 1 |SAOS:9|~841~1
- 6 - C 08 OR2 ! 0 4 0 1 |SAOS:9|:877
- 4 - C 08 OR2 ! 0 4 0 2 |SAOS:9|:913
- 2 - C 08 OR2 ! 0 4 0 4 |SAOS:9|:949
- 8 - C 08 AND2 0 4 0 4 |SAOS:9|:961
- 7 - C 08 OR2 0 4 0 1 |SAOS:9|:991
- 3 - C 08 OR2 0 4 0 1 |SAOS:9|:1059
- 7 - C 03 OR2 0 4 0 1 |SAOS:9|:1083
- 1 - C 03 OR2 0 3 0 1 |SAOS:9|:1084
- 5 - C 02 OR2 0 4 0 1 |SAOS:9|:1101
- 5 - C 03 OR2 0 4 0 1 |SAOS:9|:1150
- 5 - C 08 OR2 s 0 4 0 2 |SAOS:9|~1192~1
- 3 - C 02 AND2 s 0 3 0 2 |SAOS:9|~1246~1
- 7 - C 02 OR2 s 0 2 0 1 |SAOS:9|~1246~2
- 6 - C 02 OR2 s ! 0 2 0 1 |SAOS:9|~1254~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
shuzimiaobiao
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 17/ 96( 17%) 8/ 48( 16%) 32/ 48( 66%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
shuzimiaobiao
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 22 clk
LCELL 7 |CLKGEN:1|:34
LCELL 4 |CNT6:18|:173
LCELL 4 |CNT10:3|:173
LCELL 4 |CNT10:4|:173
LCELL 4 |CNT10:5|:173
LCELL 4 |CNT10:19|:173
Device-Specific Information: d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
shuzimiaobiao
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 clr
Device-Specific Information: d:\zhangshuhua\szmb_lastban\shuzimiaobiao.rpt
shuzimiaobiao
** EQUATIONS **
clk : INPUT;
clr : INPUT;
ena : INPUT;
-- Node name is 'duan0'
-- Equation name is 'duan0', type is output
duan0 = GND;
-- Node name is 'duan1'
-- Equation name is 'duan1', type is output
duan1 = _LC4_C3;
-- Node name is 'duan2'
-- Equation name is 'duan2', type is output
duan2 = _LC3_C3;
-- Node name is 'duan3'
-- Equation name is 'duan3', type is output
duan3 = _LC2_C3;
-- Node name is 'duan4'
-- Equation name is 'duan4', type is output
duan4 = _LC1_C2;
-- Node name is 'duan5'
-- Equation name is 'duan5', type is output
duan5 = _LC4_C2;
-- Node name is 'duan6'
-- Equation name is 'duan6', type is output
duan6 = _LC2_C2;
-- Node name is 'duan7'
-- Equation name is 'duan7', type is output
duan7 = _LC1_C8;
-- Node name is 'wei0'
-- Equation name is 'wei0', type is output
wei0 = _LC3_C15;
-- Node name is 'wei1'
-- Equation name is 'wei1', type is output
wei1 = _LC1_C12;
-- Node name is 'wei2'
-- Equation name is 'wei2', type is output
wei2 = GND;
-- Node name is 'wei3'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -