clkgen.vhd

来自「数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
   port(clk:in std_logic;
        newclk:out std_logic);
end entity clkgen;
architecture art of clkgen is 
   signal cnter:integer range 0 to 41;--频率为4096,对它进行41分频,即为0.01秒
     begin
     process(clk)is
       begin 
        if clk'event and clk='1' then
           if cnter=40 then cnter<=0;
            else cnter<=cnter+1;
           end if;
         end if;
      end process;
      process(cnter)is
        begin
         if cnter=40 then newclk<='1';
             else newclk<='0';
         end if;
      end process;
   end architecture art;