saos.rpt

交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证

-- Node name is ':769' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = LCELL( _EQ049);
  _EQ049 = !_LC4_C11 &  _LC4_C12
         #  _LC4_C11 &  p50;

-- Node name is ':772' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = LCELL( _EQ050);
  _EQ050 = !_LC3_C11 &  _LC5_C12
         #  _LC3_C11 &  p40;

-- Node name is ':775' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ051);
  _EQ051 =  _LC3_C12 & !_LC6_A4
         #  _LC6_A4 &  p30;

-- Node name is ':778' 
-- Equation name is '_LC1_C7', type is buried 
_LC1_C7  = LCELL( _EQ052);
  _EQ052 = !_LC4_C3 &  _LC8_C4
         #  _LC4_C3 &  p20;

-- Node name is ':781' 
-- Equation name is '_LC4_C7', type is buried 
_LC4_C7  = LCELL( _EQ053);
  _EQ053 =  _LC1_C7 & !_LC5_C3
         #  _LC5_C3 &  p10;

-- Node name is '~841~1' 
-- Equation name is '~841~1', location is LC2_C9, type is buried.
-- synthesized logic cell 
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ054);
  _EQ054 =  _LC3_C3
         # !_LC3_C6;

-- Node name is ':846' 
-- Equation name is '_LC6_C9', type is buried 
!_LC6_C9 = _LC6_C9~NOT;
_LC6_C9~NOT = LCELL( _EQ055);
  _EQ055 = !_LC3_C3 &  _LC3_C6 &  _LC4_C7 &  _LC5_C4
         #  _LC3_C3 &  _LC3_C6 &  _LC4_C7 & !_LC5_C4;

-- Node name is '~853~1' 
-- Equation name is '~853~1', location is LC1_B2, type is buried.
-- synthesized logic cell 
!_LC1_B2 = _LC1_B2~NOT;
_LC1_B2~NOT = LCELL( _EQ056);
  _EQ056 =  _LC5_C4
         # !_LC4_C7;

-- Node name is '~865~1' 
-- Equation name is '~865~1', location is LC8_B1, type is buried.
-- synthesized logic cell 
_LC8_B1  = LCELL( _EQ057);
  _EQ057 = !_LC4_C7 & !_LC5_C4;

-- Node name is '~889~1' 
-- Equation name is '~889~1', location is LC5_B2, type is buried.
-- synthesized logic cell 
!_LC5_B2 = _LC5_B2~NOT;
_LC5_B2~NOT = LCELL( _EQ058);
  _EQ058 = !_LC3_C3
         #  _LC3_C6;

-- Node name is '~937~1' 
-- Equation name is '~937~1', location is LC4_B2, type is buried.
-- synthesized logic cell 
!_LC4_B2 = _LC4_B2~NOT;
_LC4_B2~NOT = LCELL( _EQ059);
  _EQ059 =  _LC3_C3
         #  _LC3_C6;

-- Node name is '~949~1' 
-- Equation name is '~949~1', location is LC6_C12, type is buried.
-- synthesized logic cell 
_LC6_C12 = LCELL( _EQ060);
  _EQ060 = !_LC7_C11 & !p80 &  p81 &  p82;

-- Node name is '~949~2' 
-- Equation name is '~949~2', location is LC7_C12, type is buried.
-- synthesized logic cell 
_LC7_C12 = LCELL( _EQ061);
  _EQ061 =  _LC7_C11 & !p70 &  p71 &  p72;

-- Node name is '~949~3' 
-- Equation name is '~949~3', location is LC8_C12, type is buried.
-- synthesized logic cell 
_LC8_C12 = LCELL( _EQ062);
  _EQ062 =  _LC8_C11 & !p60 &  p61 &  p62;

-- Node name is '~949~4' 
-- Equation name is '~949~4', location is LC1_C8, type is buried.
-- synthesized logic cell 
_LC1_C8  = LCELL( _EQ063);
  _EQ063 =  _LC4_C11 & !p50 &  p51 &  p52;

-- Node name is '~949~5' 
-- Equation name is '~949~5', location is LC4_C8, type is buried.
-- synthesized logic cell 
_LC4_C8  = LCELL( _EQ064);
  _EQ064 = !p30 &  p31;

-- Node name is '~949~6' 
-- Equation name is '~949~6', location is LC3_C9, type is buried.
-- synthesized logic cell 
_LC3_C9  = LCELL( _EQ065);
  _EQ065 =  _LC4_C3 & !p20 &  p21 &  p22;

-- Node name is '~949~7' 
-- Equation name is '~949~7', location is LC5_C9, type is buried.
-- synthesized logic cell 
_LC5_C9  = LCELL( _EQ066);
  _EQ066 =  _LC5_C3 & !p10 &  p11 &  p12;

-- Node name is '~1012~1' 
-- Equation name is '~1012~1', location is LC2_B1, type is buried.
-- synthesized logic cell 
_LC2_B1  = LCELL( _EQ067);
  _EQ067 = !_LC3_C3 &  _LC3_C6 & !_LC4_C7
         #  _LC3_C3 & !_LC3_C6 &  _LC4_C7 &  _LC5_C4
         #  _LC3_C6 &  _LC4_C7 & !_LC5_C4
         # !_LC3_C3 & !_LC5_C4;

-- Node name is '~1108~1' 
-- Equation name is '~1108~1', location is LC1_C12, type is buried.
-- synthesized logic cell 
_LC1_C12 = LCELL( _EQ068);
  _EQ068 =  _LC6_C12 & !_LC8_C11
         #  _LC7_C12 & !_LC8_C11
         #  _LC8_C12;

-- Node name is '~1108~2' 
-- Equation name is '~1108~2', location is LC2_C8, type is buried.
-- synthesized logic cell 
_LC2_C8  = LCELL( _EQ069);
  _EQ069 =  _LC1_C12 & !_LC3_C11 & !_LC4_C11
         #  _LC1_C8 & !_LC3_C11;

-- Node name is '~1108~3' 
-- Equation name is '~1108~3', location is LC3_C8, type is buried.
-- synthesized logic cell 
_LC3_C8  = LCELL( _EQ070);
  _EQ070 =  _LC2_C8
         #  _LC5_C8 & !p40 &  p41;

-- Node name is '~1108~4' 
-- Equation name is '~1108~4', location is LC8_C8, type is buried.
-- synthesized logic cell 
_LC8_C8  = LCELL( _EQ071);
  _EQ071 =  _LC3_C8 & !_LC6_A4
         #  _LC4_C8 &  _LC6_A4 &  p32;

-- Node name is '~1108~5' 
-- Equation name is '~1108~5', location is LC4_C9, type is buried.
-- synthesized logic cell 
_LC4_C9  = LCELL( _EQ072);
  _EQ072 = !_LC4_C3 & !_LC5_C3 &  _LC8_C8
         #  _LC3_C9 & !_LC5_C3;

-- Node name is '~1108~6' 
-- Equation name is '~1108~6', location is LC7_C9, type is buried.
-- synthesized logic cell 
_LC7_C9  = LCELL( _EQ073);
  _EQ073 = !_LC6_C9
         #  _LC3_C3 &  _LC3_C6 &  _LC8_B1;

-- Node name is '~1108~7' 
-- Equation name is '~1108~7', location is LC8_C9, type is buried.
-- synthesized logic cell 
_LC8_C9  = LCELL( _EQ074);
  _EQ074 =  _LC3_C6 &  _LC4_C9
         #  _LC3_C6 &  _LC5_C9
         #  _LC7_C9;

-- Node name is '~1108~8' 
-- Equation name is '~1108~8', location is LC1_C9, type is buried.
-- synthesized logic cell 
_LC1_C9  = LCELL( _EQ075);
  _EQ075 =  _LC2_C9 & !_LC5_C4
         # !_LC2_C9 &  _LC8_C9
         # !_LC5_C4 &  _LC8_C9
         #  _LC4_C7 &  _LC8_C9;

-- Node name is '~1108~9' 
-- Equation name is '~1108~9', location is LC6_B2, type is buried.
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ076);
  _EQ076 =  _LC4_C7 &  _LC5_B2 & !_LC5_C4
         # !_LC4_C7 &  _LC5_B2 &  _LC5_C4
         #  _LC1_C9 & !_LC5_B2
         #  _LC1_C9 &  _LC4_C7 & !_LC5_C4
         #  _LC1_C9 & !_LC4_C7 &  _LC5_C4;

-- Node name is '~1108~10' 
-- Equation name is '~1108~10', location is LC7_B2, type is buried.
-- synthesized logic cell 
_LC7_B2  = LCELL( _EQ077);
  _EQ077 = !_LC1_B2 &  _LC3_B2
         #  _LC3_B2 & !_LC4_B2
         # !_LC1_B2 &  _LC6_B2
         # !_LC4_B2 &  _LC6_B2;

-- Node name is '~1246~1' 
-- Equation name is '~1246~1', location is LC3_B2, type is buried.
-- synthesized logic cell 
_LC3_B2  = LCELL( _EQ078);
  _EQ078 = !_LC3_C3 & !_LC3_C6 &  _LC5_C4;



Project Information                                          f:\jtdkz\saos.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,267K