📄 saos.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 04 DFFE + 0 3 1 0 :34
- 5 - A 04 DFFE + 0 3 1 0 :36
- 1 - A 04 DFFE + 0 3 1 0 :38
- 7 - C 03 DFFE + 0 3 1 0 :40
- 2 - A 04 DFFE + 0 3 1 0 :42
- 6 - C 03 DFFE + 0 3 1 0 :44
- 7 - A 04 DFFE + 0 3 1 0 :46
- 4 - A 04 DFFE + 0 3 1 0 :48
- 1 - B 01 DFFE + 0 4 1 0 :50
- 8 - B 02 DFFE + 0 4 1 0 :52
- 3 - B 01 DFFE + 0 4 1 0 :54
- 2 - B 02 DFFE + 0 4 1 0 :56
- 7 - B 01 DFFE + 0 4 1 0 :58
- 6 - B 01 DFFE + 0 4 1 0 :60
- 4 - B 01 DFFE + 0 4 1 0 :62
- 3 - A 04 DFFE + 0 2 0 15 count2 (:66)
- 1 - C 03 DFFE + 0 1 0 16 count1 (:67)
- 2 - C 03 DFFE + 0 0 0 17 count0 (:68)
- 5 - C 03 OR2 ! 0 3 0 6 :321
- 4 - C 03 OR2 ! 0 3 0 7 :325
- 6 - A 04 OR2 ! 0 3 0 5 :329
- 3 - C 11 OR2 ! 0 3 0 6 :333
- 4 - C 11 OR2 ! 0 3 0 7 :337
- 8 - C 11 OR2 ! 0 3 0 6 :341
- 7 - C 11 OR2 ! 0 3 0 6 :345
- 1 - C 06 OR2 ! 2 1 0 1 :673
- 2 - C 06 OR2 ! 1 2 0 1 :679
- 4 - C 06 OR2 ! 1 2 0 1 :685
- 5 - C 06 OR2 ! 1 2 0 1 :691
- 6 - C 06 OR2 ! 1 2 0 1 :697
- 7 - C 06 OR2 ! 1 2 0 1 :703
- 3 - C 06 OR2 ! 1 2 0 14 :709
- 2 - C 11 OR2 ! 2 1 0 1 :715
- 1 - C 11 OR2 ! 1 1 0 1 :722
- 5 - C 11 OR2 ! 1 3 0 1 :723
- 6 - C 11 OR2 ! 0 4 0 1 :724
- 5 - C 08 OR2 ! 1 1 0 2 :725
- 8 - C 03 OR2 ! 1 1 0 1 :731
- 8 - C 06 OR2 ! 1 3 0 1 :732
- 3 - C 03 OR2 ! 1 3 0 13 :733
- 1 - C 04 OR2 2 1 0 1 :739
- 2 - C 04 OR2 1 2 0 1 :742
- 3 - C 04 OR2 1 2 0 1 :745
- 4 - C 04 OR2 1 2 0 1 :748
- 6 - C 04 OR2 1 2 0 1 :751
- 7 - C 04 OR2 1 2 0 1 :754
- 5 - C 04 OR2 1 2 0 12 :757
- 2 - C 12 OR2 2 1 0 1 :763
- 4 - C 12 OR2 1 2 0 1 :766
- 5 - C 12 OR2 1 2 0 1 :769
- 3 - C 12 OR2 1 2 0 1 :772
- 8 - C 04 OR2 1 2 0 1 :775
- 1 - C 07 OR2 1 2 0 1 :778
- 4 - C 07 OR2 1 2 0 11 :781
- 2 - C 09 OR2 s ! 0 2 0 1 ~841~1
- 6 - C 09 OR2 ! 0 4 0 1 :846
- 1 - B 02 OR2 s ! 0 2 0 1 ~853~1
- 8 - B 01 AND2 s 0 2 0 3 ~865~1
- 5 - B 02 OR2 s ! 0 2 0 2 ~889~1
- 4 - B 02 OR2 s ! 0 2 0 1 ~937~1
- 6 - C 12 AND2 s 3 1 0 1 ~949~1
- 7 - C 12 AND2 s 3 1 0 1 ~949~2
- 8 - C 12 AND2 s 3 1 0 1 ~949~3
- 1 - C 08 AND2 s 3 1 0 1 ~949~4
- 4 - C 08 AND2 s 2 0 0 1 ~949~5
- 3 - C 09 AND2 s 3 1 0 1 ~949~6
- 5 - C 09 AND2 s 3 1 0 1 ~949~7
- 2 - B 01 OR2 s 0 4 0 1 ~1012~1
- 1 - C 12 OR2 s 0 4 0 1 ~1108~1
- 2 - C 08 OR2 s 0 4 0 1 ~1108~2
- 3 - C 08 OR2 s 2 2 0 1 ~1108~3
- 8 - C 08 OR2 s 1 3 0 1 ~1108~4
- 4 - C 09 OR2 s 0 4 0 1 ~1108~5
- 7 - C 09 OR2 s 0 4 0 1 ~1108~6
- 8 - C 09 OR2 s 0 4 0 1 ~1108~7
- 1 - C 09 OR2 s 0 4 0 1 ~1108~8
- 6 - B 02 OR2 s 0 4 0 1 ~1108~9
- 7 - B 02 OR2 s 0 4 0 1 ~1108~10
- 3 - B 02 AND2 s 0 3 0 2 ~1246~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 5/ 96( 5%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 23/ 96( 23%) 30/ 48( 62%) 0/ 48( 0%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 clk
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** EQUATIONS **
clk : INPUT;
p10 : INPUT;
p11 : INPUT;
p12 : INPUT;
p13 : INPUT;
p20 : INPUT;
p21 : INPUT;
p22 : INPUT;
p23 : INPUT;
p30 : INPUT;
p31 : INPUT;
p32 : INPUT;
p33 : INPUT;
p40 : INPUT;
p41 : INPUT;
p42 : INPUT;
p43 : INPUT;
p50 : INPUT;
p51 : INPUT;
p52 : INPUT;
p53 : INPUT;
p60 : INPUT;
p61 : INPUT;
p62 : INPUT;
p63 : INPUT;
p70 : INPUT;
p71 : INPUT;
p72 : INPUT;
p73 : INPUT;
p80 : INPUT;
p81 : INPUT;
p82 : INPUT;
p83 : INPUT;
-- Node name is 'choice0'
-- Equation name is 'choice0', type is output
choice0 = _LC4_A4;
-- Node name is 'choice1'
-- Equation name is 'choice1', type is output
choice1 = _LC7_A4;
-- Node name is 'choice2'
-- Equation name is 'choice2', type is output
choice2 = _LC6_C3;
-- Node name is 'choice3'
-- Equation name is 'choice3', type is output
choice3 = _LC2_A4;
-- Node name is 'choice4'
-- Equation name is 'choice4', type is output
choice4 = _LC7_C3;
-- Node name is 'choice5'
-- Equation name is 'choice5', type is output
choice5 = _LC1_A4;
-- Node name is 'choice6'
-- Equation name is 'choice6', type is output
choice6 = _LC5_A4;
-- Node name is 'choice7'
-- Equation name is 'choice7', type is output
choice7 = _LC8_A4;
-- Node name is ':68' = 'count0'
-- Equation name is 'count0', location is LC2_C3, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':67' = 'count1'
-- Equation name is 'count1', location is LC1_C3, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & !count1
# !count0 & count1;
-- Node name is ':66' = 'count2'
-- Equation name is 'count2', location is LC3_A4, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count0 & count2
# !count1 & count2
# count0 & count1 & !count2;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = GND;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC4_B1;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC6_B1;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC7_B1;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC2_B2;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC3_B1;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC8_B2;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC1_B1;
-- Node name is ':34'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = DFFE( _EQ003, GLOBAL(!clk), VCC, VCC, VCC);
_EQ003 = count0 & count1 & count2;
-- Node name is ':36'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE( _EQ004, GLOBAL(!clk), VCC, VCC, VCC);
_EQ004 = !count0 & count1 & count2;
-- Node name is ':38'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = DFFE( _EQ005, GLOBAL(!clk), VCC, VCC, VCC);
_EQ005 = count0 & !count1 & count2;
-- Node name is ':40'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = DFFE( _EQ006, GLOBAL(!clk), VCC, VCC, VCC);
_EQ006 = !count0 & !count1 & count2;
-- Node name is ':42'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = DFFE( _EQ007, GLOBAL(!clk), VCC, VCC, VCC);
_EQ007 = count0 & count1 & !count2;
-- Node name is ':44'
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