📄 saos.rpt
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Project Information f:\jtdkz\saos.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 11/29/2003 12:14:46
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SAOS
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
saos EPF10K10LC84-3 33 16 0 0 0 % 79 13 %
User Pins: 33 16 0
Project Information f:\jtdkz\saos.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':64' stuck at GND
Project Information f:\jtdkz\saos.rpt
** FILE HIERARCHY **
|lpm_add_sub:98|
|lpm_add_sub:98|addcore:adder|
|lpm_add_sub:98|altshift:result_ext_latency_ffs|
|lpm_add_sub:98|altshift:carry_ext_latency_ffs|
|lpm_add_sub:98|altshift:oflow_ext_latency_ffs|
Device-Specific Information: f:\jtdkz\saos.rpt
saos
***** Logic for device 'saos' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** ERROR SUMMARY **
Info: Chip 'saos' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
R O
c c E N
h h V G S F
o o C N E _ ^
i i C D R # D n
p p p p c c p I p p c p p I p p p V T O C
4 8 1 5 e e 2 N 7 5 l 2 1 N 3 5 5 E C N E
2 0 3 1 7 2 1 T 3 0 k 0 1 T 1 3 2 D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | choice5
^nCE | 14 72 | data0
#TDI | 15 71 | choice0
RESERVED | 16 70 | RESERVED
choice3 | 17 69 | RESERVED
choice6 | 18 68 | GNDINT
choice1 | 19 67 | RESERVED
VCCINT | 20 66 | data5
data7 | 21 65 | RESERVED
data4 | 22 EPF10K10LC84-3 64 | data3
data1 | 23 63 | VCCINT
data2 | 24 62 | p83
data6 | 25 61 | p12
GNDINT | 26 60 | p22
p72 | 27 59 | p23
p33 | 28 58 | p61
p71 | 29 57 | #TMS
choice4 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ p p p p p V G p p p V G R p R p p p R
C n 7 6 4 8 3 C N 4 1 3 C N E 6 E 4 8 6 E
C C 0 0 3 1 2 C D 0 0 0 C D S 2 S 1 2 3 S
I O I I I I E E E
N N N N N N R R R
T F T T T T V V V
I E E E
G D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A4 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 2/2 0/2 2/22( 9%)
B1 7/ 8( 87%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 4/22( 18%)
B2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
C3 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 2/2 0/2 4/22( 18%)
C4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
C6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 17/22( 77%)
C7 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C8 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
C9 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 14/22( 63%)
C11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
C12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 43/53 ( 81%)
Total logic cells used: 79/576 ( 13%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.21/4 ( 80%)
Total fan-in: 254/2304 ( 11%)
Total input pins required: 33
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 79
Total flipflops required: 18
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 24/ 576 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
B: 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15/0
C: 0 0 8 8 0 8 2 6 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 56/0
Total: 7 8 8 16 0 8 2 6 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 79/0
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
43 - - - -- INPUT 0 0 0 2 p10
83 - - - 13 INPUT 0 0 0 2 p11
61 - - C -- INPUT 0 0 0 2 p12
9 - - - 02 INPUT 0 0 0 1 p13
84 - - - -- INPUT 0 0 0 2 p20
5 - - - 05 INPUT 0 0 0 2 p21
60 - - C -- INPUT 0 0 0 2 p22
59 - - C -- INPUT 0 0 0 1 p23
44 - - - -- INPUT 0 0 0 2 p30
81 - - - 22 INPUT 0 0 0 2 p31
39 - - - 11 INPUT 0 0 0 2 p32
28 - - C -- INPUT 0 0 0 1 p33
42 - - - -- INPUT 0 0 0 2 p40
50 - - - 17 INPUT 0 0 0 2 p41
11 - - - 01 INPUT 0 0 0 1 p42
37 - - - 09 INPUT 0 0 0 1 p43
2 - - - -- INPUT 0 0 0 2 p50
8 - - - 03 INPUT 0 0 0 2 p51
79 - - - 24 INPUT 0 0 0 2 p52
80 - - - 23 INPUT 0 0 0 1 p53
36 - - - 07 INPUT 0 0 0 2 p60
58 - - C -- INPUT 0 0 0 2 p61
48 - - - 15 INPUT 0 0 0 2 p62
52 - - - 19 INPUT 0 0 0 1 p63
35 - - - 06 INPUT 0 0 0 2 p70
29 - - C -- INPUT 0 0 0 2 p71
27 - - C -- INPUT 0 0 0 2 p72
3 - - - 12 INPUT 0 0 0 1 p73
10 - - - 01 INPUT 0 0 0 2 p80
38 - - - 10 INPUT 0 0 0 2 p81
51 - - - 18 INPUT 0 0 0 2 p82
62 - - C -- INPUT 0 0 0 1 p83
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\jtdkz\saos.rpt
saos
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
71 - - A -- OUTPUT 0 1 0 0 choice0
19 - - A -- OUTPUT 0 1 0 0 choice1
6 - - - 04 OUTPUT 0 1 0 0 choice2
17 - - A -- OUTPUT 0 1 0 0 choice3
30 - - C -- OUTPUT 0 1 0 0 choice4
73 - - A -- OUTPUT 0 1 0 0 choice5
18 - - A -- OUTPUT 0 1 0 0 choice6
7 - - - 03 OUTPUT 0 1 0 0 choice7
72 - - A -- OUTPUT 0 0 0 0 data0
23 - - B -- OUTPUT 0 1 0 0 data1
24 - - B -- OUTPUT 0 1 0 0 data2
64 - - B -- OUTPUT 0 1 0 0 data3
22 - - B -- OUTPUT 0 1 0 0 data4
66 - - B -- OUTPUT 0 1 0 0 data5
25 - - B -- OUTPUT 0 1 0 0 data6
21 - - B -- OUTPUT 0 1 0 0 data7
Code:
s = Synthesized pin or logic cell
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