📄 control.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 11 AND2 0 3 0 3 |LPM_ADD_SUB:78|addcore:adder|:71
- 5 - B 11 AND2 0 2 0 1 |LPM_ADD_SUB:78|addcore:adder|:75
- 7 - B 11 DFFE + 0 3 0 1 count5 (:3)
- 4 - B 11 DFFE + 0 3 0 2 count4 (:4)
- 3 - B 11 DFFE + 0 2 0 3 count3 (:5)
- 8 - B 11 DFFE + 0 3 0 2 count2 (:6)
- 1 - B 01 DFFE + 0 2 0 3 count1 (:7)
- 8 - B 01 DFFE + 0 1 0 4 count0 (:8)
- 2 - B 11 OR2 s 0 3 0 1 ~34~1
- 6 - B 11 OR2 ! 0 4 1 6 :34
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\biyesheji\jtdkz\control.rpt
control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\biyesheji\jtdkz\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 clk
Device-Specific Information: d:\biyesheji\jtdkz\control.rpt
control
** EQUATIONS **
clk : INPUT;
-- Node name is 'clks'
-- Equation name is 'clks', type is output
clks = _LC6_B11;
-- Node name is ':8' = 'count0'
-- Equation name is 'count0', location is LC8_B1, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count0 & !_LC6_B11;
-- Node name is ':7' = 'count1'
-- Equation name is 'count1', location is LC1_B1, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count0 & !count1 & !_LC6_B11
# !count0 & count1 & !_LC6_B11;
-- Node name is ':6' = 'count2'
-- Equation name is 'count2', location is LC8_B11, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !count0 & count2 & !_LC6_B11
# !count1 & count2 & !_LC6_B11
# count0 & count1 & !count2 & !_LC6_B11;
-- Node name is ':5' = 'count3'
-- Equation name is 'count3', location is LC3_B11, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = count3 & !_LC1_B11 & !_LC6_B11
# !count3 & _LC1_B11 & !_LC6_B11;
-- Node name is ':4' = 'count4'
-- Equation name is 'count4', location is LC4_B11, type is buried.
count4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !count3 & count4 & !_LC6_B11
# count4 & !_LC1_B11 & !_LC6_B11
# count3 & !count4 & _LC1_B11 & !_LC6_B11;
-- Node name is ':3' = 'count5'
-- Equation name is 'count5', location is LC7_B11, type is buried.
count5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !count4 & count5 & !_LC6_B11
# count5 & !_LC5_B11 & !_LC6_B11
# count4 & !count5 & _LC5_B11 & !_LC6_B11;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ007);
_EQ007 = count0 & count1 & count2;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ008);
_EQ008 = count3 & _LC1_B11;
-- Node name is '~34~1'
-- Equation name is '~34~1', location is LC2_B11, type is buried.
-- synthesized logic cell
_LC2_B11 = LCELL( _EQ009);
_EQ009 = !count3
# count4
# !count5;
-- Node name is ':34'
-- Equation name is '_LC6_B11', type is buried
!_LC6_B11 = _LC6_B11~NOT;
_LC6_B11~NOT = LCELL( _EQ010);
_EQ010 = count0
# count1
# count2
# _LC2_B11;
Project Information d:\biyesheji\jtdkz\control.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,017K
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