traffic.rpt
来自「交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10K」· RPT 代码 · 共 1,404 行 · 第 1/5 页
RPT
1,404 行
Total single-pin Output Enables required: 0
Synthesized logic cells: 53/ 576 ( 9%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 8 8 8 8 8 8 8 8 8 8 1 0 1 4 1 0 6 0 2 0 1 0 0 8 112/0
C: 0 4 8 0 8 0 8 7 0 8 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47/0
Total: 8 12 16 8 16 8 16 15 8 16 12 1 0 1 4 1 0 6 0 2 0 1 0 0 8 159/0
Device-Specific Information: d:\biyesheji\jtdkz\traffic.rpt
traffic
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - -- INPUT G 0 0 0 0 clk
28 - - C -- INPUT 0 0 0 10 reset
29 - - C -- INPUT 0 0 0 16 urgen
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\biyesheji\jtdkz\traffic.rpt
traffic
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
5 - - - 05 OUTPUT 0 0 0 0 duan0
6 - - - 04 OUTPUT 0 1 0 0 duan1
7 - - - 03 OUTPUT 0 1 0 0 duan2
8 - - - 03 OUTPUT 0 1 0 0 duan3
9 - - - 02 OUTPUT 0 1 0 0 duan4
10 - - - 01 OUTPUT 0 1 0 0 duan5
11 - - - 01 OUTPUT 0 1 0 0 duan6
16 - - A -- OUTPUT 0 1 0 0 duan7
25 - - B -- OUTPUT 0 1 0 0 g1
51 - - - 18 OUTPUT 0 1 0 0 g2
23 - - B -- OUTPUT 0 1 0 0 r1
53 - - - 20 OUTPUT 0 1 0 0 r2
72 - - A -- OUTPUT 0 1 0 0 wei0
73 - - A -- OUTPUT 0 1 0 0 wei1
78 - - - 24 OUTPUT 0 1 0 0 wei2
79 - - - 24 OUTPUT 0 1 0 0 wei3
80 - - - 23 OUTPUT 0 1 0 0 wei4
81 - - - 22 OUTPUT 0 1 0 0 wei5
83 - - - 13 OUTPUT 0 1 0 0 wei6
3 - - - 12 OUTPUT 0 1 0 0 wei7
24 - - B -- OUTPUT 0 1 0 0 y1
52 - - - 19 OUTPUT 0 1 0 0 y2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\biyesheji\jtdkz\traffic.rpt
traffic
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 08 DFFE + 0 3 0 1 |CONTROL:18|count3 (|CONTROL:18|:3)
- 5 - C 08 DFFE + 0 3 0 2 |CONTROL:18|count2 (|CONTROL:18|:4)
- 6 - C 08 DFFE + 0 2 0 3 |CONTROL:18|count1 (|CONTROL:18|:5)
- 7 - C 08 DFFE + 0 0 0 4 |CONTROL:18|count0 (|CONTROL:18|:6)
- 1 - C 08 AND2 0 4 0 16 |CONTROL:18|:141
- 7 - C 05 AND2 0 3 0 3 |LEDCONTROL:1|LPM_ADD_SUB:148|addcore:adder|:71
- 6 - C 07 AND2 0 3 0 2 |LEDCONTROL:1|LPM_ADD_SUB:148|addcore:adder|:79
- 4 - C 03 DFFE 1 4 0 10 |LEDCONTROL:1|:4
- 6 - C 03 DFFE 1 5 0 9 |LEDCONTROL:1|:6
- 2 - C 02 DFFE 0 4 0 8 |LEDCONTROL:1|:9
- 8 - C 03 DFFE 0 5 0 9 |LEDCONTROL:1|:11
- 8 - C 07 DFFE 1 4 0 3 |LEDCONTROL:1|count6 (|LEDCONTROL:1|:13)
- 5 - C 07 DFFE 2 3 0 5 |LEDCONTROL:1|count5 (|LEDCONTROL:1|:14)
- 2 - C 08 DFFE 1 4 0 4 |LEDCONTROL:1|count4 (|LEDCONTROL:1|:15)
- 4 - C 07 DFFE 2 3 0 10 |LEDCONTROL:1|count3 (|LEDCONTROL:1|:16)
- 8 - C 05 DFFE 1 5 0 5 |LEDCONTROL:1|count2 (|LEDCONTROL:1|:17)
- 2 - C 10 DFFE 2 4 0 7 |LEDCONTROL:1|count1 (|LEDCONTROL:1|:18)
- 3 - C 10 DFFE 2 4 0 9 |LEDCONTROL:1|count0 (|LEDCONTROL:1|:19)
- 3 - C 02 DFFE 1 2 0 1 |LEDCONTROL:1|subtemp (|LEDCONTROL:1|:20)
- 7 - C 07 OR2 1 3 0 1 |LEDCONTROL:1|:176
- 3 - C 08 OR2 1 3 0 1 |LEDCONTROL:1|:188
- 4 - C 05 AND2 s 0 4 0 2 |LEDCONTROL:1|~228~1
- 4 - C 10 AND2 s 0 3 0 1 |LEDCONTROL:1|~228~2
- 5 - C 11 AND2 0 3 0 5 |LEDCONTROL:1|:228
- 3 - C 11 AND2 0 3 0 6 |LEDCONTROL:1|:243
- 1 - C 07 AND2 s 0 2 0 2 |LEDCONTROL:1|~258~1
- 3 - C 07 AND2 0 4 0 7 |LEDCONTROL:1|:258
- 6 - C 05 AND2 s 0 3 0 5 |LEDCONTROL:1|~273~1
- 2 - C 07 AND2 s 0 3 0 5 |LEDCONTROL:1|~273~2
- 1 - C 05 AND2 s 0 2 0 1 |LEDCONTROL:1|~288~1
- 3 - C 05 AND2 0 4 0 3 |LEDCONTROL:1|:288
- 3 - C 03 OR2 s 0 4 0 3 |LEDCONTROL:1|~357~1
- 1 - C 10 AND2 s 0 2 0 3 |LEDCONTROL:1|~377~1
- 2 - C 11 OR2 s 0 4 0 2 |LEDCONTROL:1|~431~1
- 5 - C 05 OR2 s 1 3 0 1 |LEDCONTROL:1|~449~1
- 6 - C 10 OR2 s 0 4 0 1 |LEDCONTROL:1|~467~1
- 7 - C 10 AND2 s 0 2 0 1 |LEDCONTROL:1|~467~2
- 8 - C 10 OR2 s 1 3 0 1 |LEDCONTROL:1|~467~3
- 5 - C 10 OR2 s 0 3 0 1 |LEDCONTROL:1|~483~1
- 7 - C 03 OR2 0 4 0 1 |LEDCONTROL:1|:510
- 1 - C 03 OR2 s ! 0 4 0 6 |LEDCONTROL:1|~537~1
- 1 - C 11 AND2 s ! 0 2 0 4 |LEDCONTROL:1|~537~2
- 2 - C 03 OR2 s 0 4 0 4 |LEDCONTROL:1|~549~1
- 5 - C 03 OR2 s 0 4 0 1 |LEDCONTROL:1|~555~1
- 1 - C 02 AND2 0 2 0 22 |LEDCONTROL:1|:608
- 6 - B 07 OR2 s 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:190|addcore:adder|pcarry5~1
- 3 - B 09 OR2 0 4 0 2 |LEDSHOW:2|LPM_ADD_SUB:190|addcore:adder|pcarry5
- 6 - B 11 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:190|addcore:adder|:155
- 2 - B 09 OR2 0 3 0 3 |LEDSHOW:2|LPM_ADD_SUB:231|addcore:adder|pcarry2
- 7 - B 07 OR2 0 2 0 8 |LEDSHOW:2|LPM_ADD_SUB:231|addcore:adder|pcarry3
- 1 - B 11 OR2 0 3 0 2 |LEDSHOW:2|LPM_ADD_SUB:231|addcore:adder|pcarry5
- 5 - B 09 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:231|addcore:adder|:150
- 7 - B 11 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:231|addcore:adder|:155
- 2 - B 13 OR2 s 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:553|addcore:adder|pcarry5~1
- 6 - B 05 OR2 0 4 0 2 |LEDSHOW:2|LPM_ADD_SUB:553|addcore:adder|pcarry5
- 7 - B 10 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:553|addcore:adder|:155
- 2 - B 05 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:594|addcore:adder|pcarry2
- 3 - B 05 AND2 ! 0 4 0 9 |LEDSHOW:2|LPM_ADD_SUB:594|addcore:adder|pcarry3
- 5 - B 10 OR2 0 3 0 2 |LEDSHOW:2|LPM_ADD_SUB:594|addcore:adder|pcarry5
- 4 - B 05 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:594|addcore:adder|:150
- 8 - B 10 OR2 0 3 0 1 |LEDSHOW:2|LPM_ADD_SUB:594|addcore:adder|:155
- 4 - B 17 DFFE 1 2 1 0 |LEDSHOW:2|:8
- 8 - B 17 DFFE 1 3 1 0 |LEDSHOW:2|:10
- 6 - B 17 DFFE 1 3 1 0 |LEDSHOW:2|:12
- 1 - B 19 DFFE 1 2 1 0 |LEDSHOW:2|:14
- 5 - B 17 DFFE 1 3 1 0 |LEDSHOW:2|:16
- 2 - B 19 DFFE 1 3 1 0 |LEDSHOW:2|:18
- 8 - B 11 DFFE 0 5 0 3 |LEDSHOW:2|count27 (|LEDSHOW:2|:44)
- 5 - B 11 DFFE 0 5 0 5 |LEDSHOW:2|count26 (|LEDSHOW:2|:45)
- 4 - B 11 DFFE 0 4 0 4 |LEDSHOW:2|count25 (|LEDSHOW:2|:46)
- 8 - B 07 DFFE 0 4 0 5 |LEDSHOW:2|count24 (|LEDSHOW:2|:47)
- 1 - B 07 DFFE 0 4 0 4 |LEDSHOW:2|count23 (|LEDSHOW:2|:48)
- 7 - B 09 DFFE 0 5 0 5 |LEDSHOW:2|count22 (|LEDSHOW:2|:49)
- 4 - B 09 DFFE 0 4 0 5 |LEDSHOW:2|count21 (|LEDSHOW:2|:50)
- 8 - B 09 DFFE 0 4 0 6 |LEDSHOW:2|count20 (|LEDSHOW:2|:51)
- 3 - B 10 DFFE 0 5 0 3 |LEDSHOW:2|count17 (|LEDSHOW:2|:63)
- 4 - B 10 DFFE 0 5 0 6 |LEDSHOW:2|count16 (|LEDSHOW:2|:64)
- 1 - B 10 DFFE 0 4 0 5 |LEDSHOW:2|count15 (|LEDSHOW:2|:65)
- 2 - B 10 DFFE 0 3 0 6 |LEDSHOW:2|count14 (|LEDSHOW:2|:66)
- 1 - B 05 DFFE 0 4 0 3 |LEDSHOW:2|count13 (|LEDSHOW:2|:67)
- 8 - B 05 DFFE 0 5 0 6 |LEDSHOW:2|count12 (|LEDSHOW:2|:68)
- 7 - B 05 DFFE 0 4 0 6 |LEDSHOW:2|count11 (|LEDSHOW:2|:69)
- 5 - B 05 DFFE 0 4 0 7 |LEDSHOW:2|count10 (|LEDSHOW:2|:70)
- 2 - B 11 OR2 0 4 0 1 |LEDSHOW:2|:269
- 6 - B 10 OR2 0 4 0 1 |LEDSHOW:2|:632
- 2 - C 05 OR2 ! 1 1 0 17 |LEDSHOW:2|:804
- 1 - B 17 OR2 ! 0 2 0 2 |LEDSHOW:2|:1037
- 3 - B 17 OR2 ! 0 2 0 2 |LEDSHOW:2|:1126
- 8 - C 02 SOFT s ! 1 0 0 3 reset~1
- 8 - B 12 DFFE + 0 3 1 0 |SAOS:14|:34
- 5 - B 14 DFFE + 0 3 1 0 |SAOS:14|:36
- 4 - B 21 DFFE + 0 1 1 0 |SAOS:14|:38
- 4 - B 24 DFFE + 0 1 1 0 |SAOS:14|:40
- 6 - B 24 DFFE + 0 3 1 0 |SAOS:14|:42
- 7 - B 24 DFFE + 0 3 1 0 |SAOS:14|:44
- 1 - B 15 DFFE + 0 1 1 0 |SAOS:14|:46
- 2 - B 08 DFFE + 0 1 1 0 |SAOS:14|:48
- 1 - B 02 DFFE + 0 4 1 0 |SAOS:14|:50
- 3 - B 01 DFFE + 0 4 1 0 |SAOS:14|:52
- 5 - B 01 DFFE + 0 3 1 0 |SAOS:14|:54
- 7 - B 01 DFFE + 0 4 1 0 |SAOS:14|:56
- 8 - B 04 DFFE + 0 3 1 0 |SAOS:14|:58
- 1 - B 04 DFFE + 0 4 1 0 |SAOS:14|:60
- 6 - B 04 DFFE + 0 4 1 0 |SAOS:14|:62
- 2 - B 24 DFFE + 0 2 0 9 |SAOS:14|count2 (|SAOS:14|:66)
- 1 - B 14 DFFE + 0 1 0 10 |SAOS:14|count1 (|SAOS:14|:67)
- 7 - B 14 DFFE + 0 0 0 11 |SAOS:14|count0 (|SAOS:14|:68)
- 8 - B 24 OR2 s ! 0 3 0 7 |SAOS:14|~396~1
- 3 - B 24 AND2 0 3 0 10 |SAOS:14|:572
- 5 - B 24 AND2 0 3 0 9 |SAOS:14|:576
- 1 - B 24 AND2 0 3 0 8 |SAOS:14|:588
- 8 - B 14 AND2 0 3 0 8 |SAOS:14|:592
- 3 - B 11 OR2 s 0 3 0 1 |SAOS:14|~709~1
- 2 - B 07 OR2 s 0 4 0 1 |SAOS:14|~709~2
- 3 - B 07 OR2 s ! 0 4 0 1 |SAOS:14|~709~3
- 5 - B 07 AND2 s 0 3 0 1 |SAOS:14|~709~4
- 4 - B 07 OR2 ! 0 4 0 15 |SAOS:14|:709
- 4 - B 03 OR2 ! 0 3 0 1 |SAOS:14|:722
- 6 - B 03 OR2 ! 0 3 0 1 |SAOS:14|:723
- 3 - B 03 OR2 ! 0 4 0 1 |SAOS:14|:730
- 2 - B 03 OR2 ! 0 3 0 1 |SAOS:14|:731
- 1 - B 01 OR2 ! 0 4 0 14 |SAOS:14|:733
- 6 - B 09 OR2 s ! 0 3 0 1 |SAOS:14|~757~1
- 4 - B 08 OR2 s ! 0 4 0 1 |SAOS:14|~757~2
- 5 - B 08 OR2 s ! 0 3 0 1 |SAOS:14|~757~3
- 7 - B 08 OR2 s ! 0 4 0 1 |SAOS:14|~757~4
- 6 - B 08 OR2 0 4 0 14 |SAOS:14|:757
- 1 - B 03 OR2 s ! 0 3 0 1 |SAOS:14|~781~1
- 7 - B 03 OR2 s ! 0 4 0 1 |SAOS:14|~781~2
- 1 - B 08 OR2 s ! 0 3 0 1 |SAOS:14|~781~3
- 3 - B 08 OR2 s ! 0 4 0 1 |SAOS:14|~781~4
- 8 - B 08 OR2 0 4 0 13 |SAOS:14|:781
- 6 - B 02 AND2 0 4 0 1 |SAOS:14|:817
- 4 - B 02 OR2 s ! 0 2 0 1 |SAOS:14|~841~1
- 5 - B 02 OR2 ! 0 4 0 1 |SAOS:14|:846
- 3 - B 02 OR2 s ! 0 2 0 1 |SAOS:14|~889~1
- 3 - B 04 AND2 0 4 0 1 |SAOS:14|:913
- 3 - B 06 AND2 s 0 2 0 1 |SAOS:14|~949~1
- 5 - B 06 AND2 s 0 3 0 1 |SAOS:14|~949~2
- 8 - B 06 AND2 s 0 4 0 1 |SAOS:14|~949~3
- 8 - B 01 OR2 ! 0 4 0 5 |SAOS:14|:949
- 4 - B 01 OR2 ! 0 4 0 5 |SAOS:14|:961
- 2 - B 01 OR2 0 4 0 1 |SAOS:14|:1059
- 5 - B 03 OR2 s 0 4 0 1 |SAOS:14|~1108~1
- 8 - B 03 OR2 s 0 4 0 1 |SAOS:14|~1108~2
- 1 - B 09 OR2 s 0 4 0 1 |SAOS:14|~1108~3
- 1 - B 06 OR2 s 0 4 0 1 |SAOS:14|~1108~4
- 2 - B 06 OR2 s 0 4 0 1 |SAOS:14|~1108~5
- 4 - B 06 OR2 s 0 4 0 1 |SAOS:14|~1108~6
- 7 - B 06 OR2 s 0 4 0 1 |SAOS:14|~1108~7
- 6 - B 06 OR2 s 0 4 0 1 |SAOS:14|~1108~8
- 7 - B 02 OR2 s 0 4 0 1 |SAOS:14|~1108~9
- 8 - B 02 OR2 s 0 4 0 1 |SAOS:14|~1108~10
- 2 - B 02 OR2 s 0 4 0 1 |SAOS:14|~1108~11
- 7 - B 04 OR2 0 4 0 1 |SAOS:14|:1150
- 5 - B 04 OR2 0 4 0 1 |SAOS:14|:1192
- 6 - B 01 AND2 s 0 3 0 3 |SAOS:14|~1246~1
- 4 - B 04 OR2 s 0 4 0 1 |SAOS:14|~1246~2
- 2 - B 04 AND2 s 0 2 0 1 |SAOS:14|~1254~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\biyesheji\jtdkz\traffic.rpt
traffic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 21/ 96( 21%) 39/ 48( 81%) 5/ 48( 10%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 3/ 96( 3%) 21/ 48( 43%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
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