ledcontrol.rpt

交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证

         #  count6;

-- Node name is '~228~2' 
-- Equation name is '~228~2', location is LC3_C24, type is buried.
-- synthesized logic cell 
_LC3_C24 = LCELL( _EQ017);
  _EQ017 = !count0 &  _LC3_C20 & !_LC5_C13;

-- Node name is ':228' 
-- Equation name is '_LC2_C21', type is buried 
!_LC2_C21 = _LC2_C21~NOT;
_LC2_C21~NOT = LCELL( _EQ018);
  _EQ018 =  count3
         #  count5
         #  count1
         #  _LC5_C21;

-- Node name is ':243' 
-- Equation name is '_LC4_C21', type is buried 
!_LC4_C21 = _LC4_C21~NOT;
_LC4_C21~NOT = LCELL( _EQ019);
  _EQ019 = !count3
         # !count5
         #  count1
         #  _LC5_C21;

-- Node name is '~258~1' 
-- Equation name is '~258~1', location is LC4_C13, type is buried.
-- synthesized logic cell 
!_LC4_C13 = _LC4_C13~NOT;
_LC4_C13~NOT = LCELL( _EQ020);
  _EQ020 =  count3 &  count5;

-- Node name is ':258' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ021);
  _EQ021 = !count4 & !count6 & !_LC4_C13 &  _LC5_C16;

-- Node name is '~273~1' 
-- Equation name is '~273~1', location is LC5_C16, type is buried.
-- synthesized logic cell 
_LC5_C16 = LCELL( _EQ022);
  _EQ022 =  count0 & !count1 &  count2;

-- Node name is '~273~2' 
-- Equation name is '~273~2', location is LC1_C21, type is buried.
-- synthesized logic cell 
_LC1_C21 = LCELL( _EQ023);
  _EQ023 =  count4 & !count5 &  count6;

-- Node name is '~288~1' 
-- Equation name is '~288~1', location is LC1_C20, type is buried.
-- synthesized logic cell 
_LC1_C20 = LCELL( _EQ024);
  _EQ024 =  count0
         #  count2;

-- Node name is ':288' 
-- Equation name is '_LC4_C20', type is buried 
!_LC4_C20 = _LC4_C20~NOT;
_LC4_C20~NOT = LCELL( _EQ025);
  _EQ025 = !count3
         # !count1
         # !_LC1_C21
         #  _LC1_C20;

-- Node name is '~357~1' 
-- Equation name is '~357~1', location is LC6_C20, type is buried.
-- synthesized logic cell 
_LC6_C20 = LCELL( _EQ026);
  _EQ026 = !_LC4_C20
         # !count3 &  _LC1_C21 &  _LC5_C16;

-- Node name is '~387~1' 
-- Equation name is '~387~1', location is LC3_C20, type is buried.
-- synthesized logic cell 
_LC3_C20 = LCELL( _EQ027);
  _EQ027 =  count3 & !_LC4_C20
         # !_LC1_C21 & !_LC4_C20
         # !_LC4_C20 & !_LC5_C16;

-- Node name is '~413~1' 
-- Equation name is '~413~1', location is LC6_C13, type is buried.
-- synthesized logic cell 
_LC6_C13 = LCELL( _EQ028);
  _EQ028 = !_LC2_C21 & !_LC4_C21;

-- Node name is '~431~1' 
-- Equation name is '~431~1', location is LC7_C13, type is buried.
-- synthesized logic cell 
_LC7_C13 = LCELL( _EQ029);
  _EQ029 = !_LC2_C21 &  _LC5_C13
         # !_LC2_C21 &  _LC4_C21
         # !_LC2_C21 &  _LC3_C20;

-- Node name is '~449~1' 
-- Equation name is '~449~1', location is LC1_C24, type is buried.
-- synthesized logic cell 
_LC1_C24 = LCELL( _EQ030);
  _EQ030 =  count2 &  urgen
         # !count1 &  count2
         # !count0 &  count2
         #  count0 &  count1 & !count2 & !urgen;

-- Node name is '~467~1' 
-- Equation name is '~467~1', location is LC5_C24, type is buried.
-- synthesized logic cell 
_LC5_C24 = LCELL( _EQ031);
  _EQ031 =  _LC3_C20 & !_LC5_C13;

-- Node name is '~467~2' 
-- Equation name is '~467~2', location is LC6_C24, type is buried.
-- synthesized logic cell 
_LC6_C24 = LCELL( _EQ032);
  _EQ032 =  count1 &  _LC5_C24 &  urgen
         # !count0 &  count1 &  _LC5_C24;

-- Node name is '~467~3' 
-- Equation name is '~467~3', location is LC7_C24, type is buried.
-- synthesized logic cell 
_LC7_C24 = LCELL( _EQ033);
  _EQ033 =  count0 & !count1 &  _LC3_C20
         #  _LC2_C20;

-- Node name is '~483~1' 
-- Equation name is '~483~1', location is LC4_C24, type is buried.
-- synthesized logic cell 
_LC4_C24 = LCELL( _EQ034);
  _EQ034 =  count0 &  _LC3_C20
         #  _LC2_C20;

-- Node name is '~495~1' 
-- Equation name is '~495~1', location is LC2_C20, type is buried.
-- synthesized logic cell 
_LC2_C20 = LCELL( _EQ035);
  _EQ035 = !count3 &  _LC1_C21 &  _LC5_C16
         #  _LC5_C13;

-- Node name is ':510' 
-- Equation name is '_LC8_C13', type is buried 
_LC8_C13 = LCELL( _EQ036);
  _EQ036 =  _LC3_C13
         # !count3 &  _LC1_C21 &  _LC5_C16;

-- Node name is '~537~1' 
-- Equation name is '~537~1', location is LC4_C23, type is buried.
-- synthesized logic cell 
!_LC4_C23 = _LC4_C23~NOT;
_LC4_C23~NOT = LCELL( _EQ037);
  _EQ037 = !_LC5_C13 &  _LC6_C13;

-- Node name is '~555~1' 
-- Equation name is '~555~1', location is LC5_C20, type is buried.
-- synthesized logic cell 
_LC5_C20 = LCELL( _EQ038);
  _EQ038 =  _LC2_C20 & !_LC4_C21
         #  _LC4_C20 &  _LC8_C20
         #  _LC4_C21 &  _LC8_C20;

-- Node name is ':608' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ039);
  _EQ039 = !clk &  subtemp;



Project Information                                f:\eda\jtdkz\ledcontrol.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,408K