📄 ledcontrol.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 16 AND2 0 3 0 3 |LPM_ADD_SUB:148|addcore:adder|:71
- 6 - C 21 AND2 0 3 0 2 |LPM_ADD_SUB:148|addcore:adder|:79
- 5 - C 23 SOFT s ! 1 0 0 3 reset~1
- 1 - C 13 DFFE + 0 3 1 0 :4
- 3 - C 13 DFFE + 0 4 1 1 :6
- 7 - C 23 DFFE + 0 3 1 0 :9
- 8 - C 20 DFFE + 0 3 1 1 :11
- 3 - C 21 DFFE + 0 3 0 4 count6 (:13)
- 8 - C 21 DFFE + 1 2 0 5 count5 (:14)
- 2 - C 23 DFFE + 0 3 0 5 count4 (:15)
- 2 - C 13 DFFE + 1 2 0 10 count3 (:16)
- 6 - C 23 DFFE + 0 4 0 5 count2 (:17)
- 8 - C 24 DFFE + 1 3 0 8 count1 (:18)
- 2 - C 24 DFFE + 1 3 0 9 count0 (:19)
- 8 - C 23 DFFE + 1 1 0 1 subtemp (:20)
- 7 - C 21 OR2 1 3 0 1 :176
- 1 - C 23 OR2 1 3 0 1 :188
- 5 - C 21 OR2 s 0 4 0 2 ~228~1
- 3 - C 24 AND2 s 0 3 0 1 ~228~2
- 2 - C 21 OR2 ! 0 4 0 5 :228
- 4 - C 21 OR2 ! 0 4 0 5 :243
- 4 - C 13 AND2 s ! 0 2 0 1 ~258~1
- 5 - C 13 AND2 0 4 0 7 :258
- 5 - C 16 AND2 s 0 3 0 5 ~273~1
- 1 - C 21 AND2 s 0 3 0 5 ~273~2
- 1 - C 20 OR2 s 0 2 0 1 ~288~1
- 4 - C 20 OR2 ! 0 4 0 3 :288
- 6 - C 20 OR2 s 0 4 0 3 ~357~1
- 3 - C 20 OR2 s 0 4 0 6 ~387~1
- 6 - C 13 AND2 s 0 2 0 4 ~413~1
- 7 - C 13 OR2 s 0 4 0 2 ~431~1
- 1 - C 24 OR2 s 1 3 0 1 ~449~1
- 5 - C 24 AND2 s 0 2 0 1 ~467~1
- 6 - C 24 OR2 s 1 3 0 1 ~467~2
- 7 - C 24 OR2 s 0 4 0 1 ~467~3
- 4 - C 24 OR2 s 0 3 0 1 ~483~1
- 2 - C 20 OR2 s 0 4 0 4 ~495~1
- 8 - C 13 OR2 0 4 0 1 :510
- 4 - C 23 AND2 s ! 0 2 0 3 ~537~1
- 5 - C 20 OR2 s 0 4 0 1 ~555~1
- 3 - C 23 AND2 1 1 1 0 :608
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda\jtdkz\ledcontrol.rpt
ledcontrol
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 25/ 48( 52%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda\jtdkz\ledcontrol.rpt
ledcontrol
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
Device-Specific Information: f:\eda\jtdkz\ledcontrol.rpt
ledcontrol
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 10 reset
Device-Specific Information: f:\eda\jtdkz\ledcontrol.rpt
ledcontrol
** EQUATIONS **
clk : INPUT;
reset : INPUT;
urgen : INPUT;
-- Node name is ':19' = 'count0'
-- Equation name is 'count0', location is LC2_C24, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = _LC3_C24 & !urgen
# !_LC6_C13 & !urgen
# _LC4_C24 & _LC6_C13 & urgen;
-- Node name is ':18' = 'count1'
-- Equation name is 'count1', location is LC8_C24, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = _LC6_C13 & _LC6_C24
# _LC6_C13 & _LC7_C24 & !urgen;
-- Node name is ':17' = 'count2'
-- Equation name is 'count2', location is LC6_C23, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = _LC1_C24 & _LC5_C13 & _LC6_C13
# _LC1_C24 & _LC6_C13 & _LC6_C20;
-- Node name is ':16' = 'count3'
-- Equation name is 'count3', location is LC2_C13, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = count3 & _LC7_C13 & urgen
# count3 & !_LC1_C16 & _LC7_C13
# !count3 & _LC1_C16 & _LC7_C13 & !urgen;
-- Node name is ':15' = 'count4'
-- Equation name is 'count4', location is LC2_C23, type is buried.
count4 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ005 = _LC1_C23 & !_LC4_C23 & _LC6_C20;
-- Node name is ':14' = 'count5'
-- Equation name is 'count5', location is LC8_C21, type is buried.
count5 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ006 = count5 & _LC7_C13 & urgen
# count5 & !_LC6_C21 & _LC7_C13
# !count5 & _LC6_C21 & _LC7_C13 & !urgen;
-- Node name is ':13' = 'count6'
-- Equation name is 'count6', location is LC3_C21, type is buried.
count6 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC4_C23 & _LC6_C20 & _LC7_C21;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC5_C23, type is buried.
-- synthesized logic cell
!_LC5_C23 = _LC5_C23~NOT;
_LC5_C23~NOT = LCELL(!reset);
-- Node name is 'set1'
-- Equation name is 'set1', type is output
set1 = _LC7_C23;
-- Node name is 'set2'
-- Equation name is 'set2', type is output
set2 = _LC8_C20;
-- Node name is 'state0'
-- Equation name is 'state0', type is output
state0 = _LC3_C13;
-- Node name is 'state1'
-- Equation name is 'state1', type is output
state1 = _LC1_C13;
-- Node name is 'sub'
-- Equation name is 'sub', type is output
sub = _LC3_C23;
-- Node name is ':20' = 'subtemp'
-- Equation name is 'subtemp', location is LC8_C23, type is buried.
subtemp = DFFE(!urgen, GLOBAL( clk), VCC, VCC, !_LC5_C23);
-- Node name is '|LPM_ADD_SUB:148|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = LCELL( _EQ008);
_EQ008 = count0 & count1 & count2;
-- Node name is '|LPM_ADD_SUB:148|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ009);
_EQ009 = count3 & count4 & _LC1_C16;
-- Node name is ':4'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = DFFE( _EQ010, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ010 = _LC1_C13 & !_LC2_C21 & !_LC4_C21
# _LC2_C20 & !_LC2_C21 & !_LC4_C21;
-- Node name is ':6'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = DFFE( _EQ011, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ011 = !_LC2_C21 & !_LC5_C13 & _LC8_C13
# !_LC2_C21 & _LC4_C21;
-- Node name is ':9'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, !_LC5_C23);
_EQ012 = !_LC3_C20 & _LC7_C23
# _LC4_C23;
-- Node name is ':11'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, !_LC5_C23);
_EQ013 = _LC5_C20
# _LC2_C21;
-- Node name is ':176'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ014);
_EQ014 = !count5 & count6
# count6 & !_LC6_C21
# count5 & !count6 & _LC6_C21 & !urgen
# count6 & urgen;
-- Node name is ':188'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ015);
_EQ015 = !count3 & count4
# count4 & !_LC1_C16
# count3 & !count4 & _LC1_C16 & !urgen
# count4 & urgen;
-- Node name is '~228~1'
-- Equation name is '~228~1', location is LC5_C21, type is buried.
-- synthesized logic cell
_LC5_C21 = LCELL( _EQ016);
_EQ016 = count0
# count2
# count4
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