📄 control.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity control is
port ( clk : in std_logic;
clks :out std_logic);
end control;
architecture aa of control is
signal count : integer range 0 to 41;
begin
PROCESS (clk)
BEGIN
IF clk'event and clk='1' THEN
if count=40 then count<=0;
else count<=count+1;
end if;
END IF;
END PROCESS;
PROCESS (count)
BEGIN
IF count=40 then clks<='1';
else clks<='0';
END IF;
END PROCESS;
end aa;
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