ledshow.rpt

交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证

-- Node name is '|LPM_ADD_SUB:231|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A9', type is buried 
_LC3_A9  = LCELL( _EQ022);
  _EQ022 = !count20 & !count21 &  count22
         #  count21 & !count22
         #  count20 & !count22;

-- Node name is '|LPM_ADD_SUB:231|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_A5', type is buried 
_LC8_A5  = LCELL( _EQ023);
  _EQ023 = !count26 &  count27 & !_LC4_A5
         #  count26 & !count27
         # !count27 &  _LC4_A5;

-- Node name is '|LPM_ADD_SUB:553|addcore:adder|pcarry5~1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B3', type is buried 
-- synthesized logic cell 
_LC7_B3  = LCELL( _EQ024);
  _EQ024 =  count14
         #  count13
         #  count15;

-- Node name is '|LPM_ADD_SUB:553|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = LCELL( _EQ025);
  _EQ025 =  count10 &  count11 &  count12
         #  _LC7_B3;

-- Node name is '|LPM_ADD_SUB:553|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ026);
  _EQ026 = !count16 &  count17 & !_LC1_B3
         #  count16 & !count17
         # !count17 &  _LC1_B3;

-- Node name is '|LPM_ADD_SUB:594|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B3', type is buried 
_LC6_B3  = LCELL( _EQ027);
  _EQ027 =  count11
         #  count10
         #  count12;

-- Node name is '|LPM_ADD_SUB:594|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ028);
  _EQ028 =  count14
         # !_LC8_B3
         #  count15;

-- Node name is '|LPM_ADD_SUB:594|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ029);
  _EQ029 = !count10 & !count11 &  count12
         #  count11 & !count12
         #  count10 & !count12;

-- Node name is '|LPM_ADD_SUB:594|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ030);
  _EQ030 = !count16 &  count17 & !_LC2_B5
         #  count16 & !count17
         # !count17 &  _LC2_B5;

-- Node name is ':8' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = DFFE( _EQ031, GLOBAL( sub),  VCC,  VCC,  VCC);
  _EQ031 =  urgen
         #  state1;

-- Node name is ':10' 
-- Equation name is '_LC4_B11', type is buried 
_LC4_B11 = DFFE( _EQ032, GLOBAL( sub),  VCC,  VCC,  VCC);
  _EQ032 = !state0 & !state1 & !urgen;

-- Node name is ':12' 
-- Equation name is '_LC1_B11', type is buried 
_LC1_B11 = DFFE( _EQ033, GLOBAL( sub),  VCC,  VCC,  VCC);
  _EQ033 =  state0 & !state1 & !urgen;

-- Node name is ':14' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = DFFE( _EQ034, GLOBAL( sub),  VCC,  VCC,  VCC);
  _EQ034 =  urgen
         # !state1;

-- Node name is ':16' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = DFFE( _EQ035, GLOBAL( sub),  VCC,  VCC,  VCC);
  _EQ035 = !state0 &  state1 & !urgen;

-- Node name is ':18' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = DFFE( _EQ036, GLOBAL( sub),  VCC,  VCC,  VCC);
  _EQ036 =  state0 &  state1 & !urgen;

-- Node name is ':129' 
-- Equation name is '_LC1_A9', type is buried 
!_LC1_A9 = _LC1_A9~NOT;
_LC1_A9~NOT = LCELL( _EQ037);
  _EQ037 =  count23
         #  count22
         #  count21
         #  count20;

-- Node name is ':269' 
-- Equation name is '_LC5_A5', type is buried 
_LC5_A5  = LCELL( _EQ038);
  _EQ038 =  count26 & !_LC1_A9 &  _LC4_A5
         # !count26 & !_LC1_A9 & !_LC4_A5
         #  count26 &  _LC1_A9 &  _LC4_A9
         # !count26 &  _LC1_A9 & !_LC4_A9;

-- Node name is ':492' 
-- Equation name is '_LC8_B3', type is buried 
!_LC8_B3 = _LC8_B3~NOT;
_LC8_B3~NOT = LCELL( _EQ039);
  _EQ039 =  count13
         #  count12
         #  count11
         #  count10;

-- Node name is ':632' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ040);
  _EQ040 =  count16 &  _LC2_B5 & !_LC8_B3
         # !count16 & !_LC2_B5 & !_LC8_B3
         #  count16 &  _LC1_B3 &  _LC8_B3
         # !count16 & !_LC1_B3 &  _LC8_B3;

-- Node name is ':814' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = LCELL( _EQ041);
  _EQ041 = !clk &  urgen
         #  count17;

-- Node name is ':820' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ042);
  _EQ042 = !clk &  urgen
         #  count16;

-- Node name is ':826' 
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = LCELL( _EQ043);
  _EQ043 = !clk &  urgen
         #  count15;

-- Node name is ':832' 
-- Equation name is '_LC8_B11', type is buried 
_LC8_B11 = LCELL( _EQ044);
  _EQ044 = !clk &  urgen
         #  count14;

-- Node name is ':838' 
-- Equation name is '_LC3_B6', type is buried 
_LC3_B6  = LCELL( _EQ045);
  _EQ045 = !clk &  urgen
         #  count13;

-- Node name is ':844' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = LCELL( _EQ046);
  _EQ046 = !clk &  urgen
         #  count12;

-- Node name is ':850' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = LCELL( _EQ047);
  _EQ047 = !clk &  urgen
         #  count11;

-- Node name is ':856' 
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = LCELL( _EQ048);
  _EQ048 = !clk &  urgen
         #  count10;

-- Node name is ':873' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = LCELL( _EQ049);
  _EQ049 = !clk &  urgen
         #  count27;

-- Node name is ':879' 
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = LCELL( _EQ050);
  _EQ050 = !clk &  urgen
         #  count26;

-- Node name is ':885' 
-- Equation name is '_LC5_B6', type is buried 
_LC5_B6  = LCELL( _EQ051);
  _EQ051 = !clk &  urgen
         #  count25;

-- Node name is ':891' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ052);
  _EQ052 = !clk &  urgen
         #  count24;

-- Node name is ':897' 
-- Equation name is '_LC7_B6', type is buried 
_LC7_B6  = LCELL( _EQ053);
  _EQ053 = !clk &  urgen
         #  count23;

-- Node name is ':903' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ054);
  _EQ054 = !clk &  urgen
         #  count22;

-- Node name is ':909' 
-- Equation name is '_LC5_A9', type is buried 
_LC5_A9  = LCELL( _EQ055);
  _EQ055 = !clk &  urgen
         #  count21;

-- Node name is ':915' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ056);
  _EQ056 = !clk &  urgen
         #  count20;

-- Node name is ':1037' 
-- Equation name is '_LC5_B11', type is buried 
!_LC5_B11 = _LC5_B11~NOT;
_LC5_B11~NOT = LCELL( _EQ057);
  _EQ057 =  state1
         #  state0;

-- Node name is ':1126' 
-- Equation name is '_LC4_A2', type is buried 
!_LC4_A2 = _LC4_A2~NOT;
_LC4_A2~NOT = LCELL( _EQ058);
  _EQ058 = !state1
         #  state0;



Project Information                                   f:\eda\jtdkz\ledshow.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,921K