reg32b.vhd

8位十进制频率计,通过验证,目标芯片EPF10KLC84-4

library ieee;
use ieee.std_logic_1164.all;
entity reg32b is
port(load:in std_logic;
     din:in std_logic_vector(31 downto 0);
     dout:out std_logic_vector(31 downto 0));
end entity reg32b;
architecture art of reg32b is
begin
  process(load,din)is
    begin
    if load'event and load='1' then
      dout<=din;
    end if;
  end process;
end architecture art;