📄 clkgen.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\clkgen.rpt
clkgen
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\clkgen.rpt
clkgen
** EQUATIONS **
clk : INPUT;
-- Node name is ':13' = 'cnter0'
-- Equation name is 'cnter0', location is LC1_C7, type is buried.
cnter0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cnter0 & !_LC7_C8;
-- Node name is ':12' = 'cnter1'
-- Equation name is 'cnter1', location is LC2_C7, type is buried.
cnter1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = cnter0 & !cnter1 & !_LC7_C8
# !cnter0 & cnter1 & !_LC7_C8;
-- Node name is ':11' = 'cnter2'
-- Equation name is 'cnter2', location is LC7_C4, type is buried.
cnter2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = cnter2 & !_LC4_C7 & !_LC7_C8
# !cnter2 & _LC4_C7 & !_LC7_C8;
-- Node name is ':10' = 'cnter3'
-- Equation name is 'cnter3', location is LC6_C4, type is buried.
cnter3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !cnter2 & cnter3 & !_LC7_C8
# cnter3 & !_LC4_C7 & !_LC7_C8
# cnter2 & !cnter3 & _LC4_C7 & !_LC7_C8;
-- Node name is ':9' = 'cnter4'
-- Equation name is 'cnter4', location is LC4_C4, type is buried.
cnter4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = cnter4 & !_LC2_C4 & !_LC7_C8
# !cnter4 & _LC2_C4 & !_LC7_C8;
-- Node name is ':8' = 'cnter5'
-- Equation name is 'cnter5', location is LC5_C4, type is buried.
cnter5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !cnter4 & cnter5 & !_LC7_C8
# cnter5 & !_LC2_C4 & !_LC7_C8
# cnter4 & !cnter5 & _LC2_C4 & !_LC7_C8;
-- Node name is ':7' = 'cnter6'
-- Equation name is 'cnter6', location is LC5_C7, type is buried.
cnter6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = cnter6 & !_LC1_C4 & !_LC7_C8
# !cnter6 & _LC1_C4 & !_LC7_C8;
-- Node name is ':6' = 'cnter7'
-- Equation name is 'cnter7', location is LC8_C8, type is buried.
cnter7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !cnter6 & cnter7 & !_LC7_C8
# cnter7 & !_LC1_C4 & !_LC7_C8
# cnter6 & !cnter7 & _LC1_C4 & !_LC7_C8;
-- Node name is ':5' = 'cnter8'
-- Equation name is 'cnter8', location is LC3_C8, type is buried.
cnter8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = cnter8 & !_LC2_C8 & !_LC7_C8
# !cnter8 & _LC2_C8 & !_LC7_C8;
-- Node name is ':4' = 'cnter9'
-- Equation name is 'cnter9', location is LC4_C8, type is buried.
cnter9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !cnter8 & cnter9 & !_LC7_C8
# cnter9 & !_LC2_C8 & !_LC7_C8
# cnter8 & !cnter9 & _LC2_C8 & !_LC7_C8;
-- Node name is ':3' = 'cnter10'
-- Equation name is 'cnter10', location is LC6_C8, type is buried.
cnter10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !cnter9 & cnter10 & !_LC7_C8
# cnter10 & !_LC5_C8 & !_LC7_C8
# cnter9 & !cnter10 & _LC5_C8 & !_LC7_C8;
-- Node name is 'newclk'
-- Equation name is 'newclk', type is output
newclk = _LC7_C8;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = LCELL( _EQ012);
_EQ012 = cnter0 & cnter1;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ013);
_EQ013 = cnter2 & cnter3 & _LC4_C7;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ014);
_EQ014 = cnter4 & cnter5 & _LC2_C4;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ015);
_EQ015 = cnter6 & cnter7 & _LC1_C4;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ016);
_EQ016 = cnter8 & _LC2_C8;
-- Node name is '~59~1'
-- Equation name is '~59~1', location is LC1_C8, type is buried.
-- synthesized logic cell
_LC1_C8 = LCELL( _EQ017);
_EQ017 = cnter8
# cnter9
# !cnter10;
-- Node name is '~59~2'
-- Equation name is '~59~2', location is LC3_C4, type is buried.
-- synthesized logic cell
_LC3_C4 = LCELL( _EQ018);
_EQ018 = cnter4
# cnter5
# cnter6;
-- Node name is '~59~3'
-- Equation name is '~59~3', location is LC8_C4, type is buried.
-- synthesized logic cell
_LC8_C4 = LCELL( _EQ019);
_EQ019 = cnter3
# _LC3_C4
# cnter1
# cnter2;
-- Node name is ':59'
-- Equation name is '_LC7_C8', type is buried
!_LC7_C8 = _LC7_C8~NOT;
_LC7_C8~NOT = LCELL( _EQ020);
_EQ020 = cnter0
# cnter7
# _LC1_C8
# _LC8_C4;
Project Information f:\zhangshuhua\keneishiyan\shiyan10\clkgen.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,478K
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