dongtai8duankou.rpt

8位十进制频率计,通过验证,目标芯片EPF10KLC84-4

         # !_LC1_B21 & !_LC2_A3
         # !_LC2_A3 & !_LC3_A10;

-- Node name is '~1534~2' 
-- Equation name is '~1534~2', location is LC1_A12, type is buried.
-- synthesized logic cell 
!_LC1_A12 = _LC1_A12~NOT;
_LC1_A12~NOT = LCELL( _EQ057);
  _EQ057 = !_LC1_A9 & !_LC3_A10
         # !_LC1_A9 &  _LC1_B21 &  _LC1_C20;

-- Node name is '~1534~3' 
-- Equation name is '~1534~3', location is LC6_A3, type is buried.
-- synthesized logic cell 
!_LC6_A3 = _LC6_A3~NOT;
_LC6_A3~NOT = LCELL( _EQ058);
  _EQ058 =  _LC1_C20
         # !_LC3_A10;

-- Node name is ':1534' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ059);
  _EQ059 = !_LC4_A3 &  _LC7_A6
         # !_LC4_A3 &  _LC8_A6
         #  _LC1_A12;

-- Node name is ':1546' 
-- Equation name is '_LC4_A9', type is buried 
_LC4_A9  = LCELL( _EQ060);
  _EQ060 = !_LC2_A8 &  _LC5_A9
         #  _LC4_A10;

-- Node name is ':1573' 
-- Equation name is '_LC6_A9', type is buried 
_LC6_A9  = LCELL( _EQ061);
  _EQ061 = !_LC2_A2 &  _LC4_A9
         #  _LC2_A6
         #  _LC1_A9;

-- Node name is ':1582' 
-- Equation name is '_LC5_A9', type is buried 
_LC5_A9  = LCELL( _EQ062);
  _EQ062 = !_LC1_C20 &  _LC3_A10
         # !_LC1_C20 &  _LC6_A9
         #  _LC1_B21 &  _LC6_A9
         # !_LC3_A10 &  _LC6_A9;

-- Node name is '~1597~1' 
-- Equation name is '~1597~1', location is LC6_A10, type is buried.
-- synthesized logic cell 
!_LC6_A10 = _LC6_A10~NOT;
_LC6_A10~NOT = LCELL( _EQ063);
  _EQ063 = !_LC4_B14
         # !_LC1_C20 & !_LC8_A10
         # !_LC1_B21 & !_LC8_A10
         # !_LC1_B21 & !_LC1_C20
         #  _LC1_B21 &  _LC1_C20 &  _LC8_A10;

-- Node name is ':1597' 
-- Equation name is '_LC6_A8', type is buried 
_LC6_A8  = LCELL( _EQ064);
  _EQ064 = !_LC4_A8 &  _LC5_A8
         #  _LC6_A10;

-- Node name is ':1606' 
-- Equation name is '_LC7_A8', type is buried 
_LC7_A8  = LCELL( _EQ065);
  _EQ065 = !_LC1_C20 &  _LC2_A10
         # !_LC1_C20 &  _LC6_A8
         #  _LC1_B21 &  _LC6_A8
         # !_LC2_A10 &  _LC6_A8;

-- Node name is ':1623' 
-- Equation name is '_LC8_A8', type is buried 
_LC8_A8  = LCELL( _EQ066);
  _EQ066 = !_LC2_A3 & !_LC3_A3 &  _LC7_A8
         # !_LC2_A3 &  _LC4_A3;

-- Node name is ':1630' 
-- Equation name is '_LC5_A8', type is buried 
_LC5_A8  = LCELL( _EQ067);
  _EQ067 =  _LC1_C20 &  _LC3_A10
         # !_LC1_B21 &  _LC3_A10
         #  _LC1_C20 &  _LC8_A8
         # !_LC1_B21 &  _LC8_A8
         # !_LC3_A10 &  _LC8_A8;

-- Node name is '~1648~1' 
-- Equation name is '~1648~1', location is LC2_A9, type is buried.
-- synthesized logic cell 
_LC2_A9  = LCELL( _EQ068);
  _EQ068 =  _LC2_A8
         #  _LC4_A10;

-- Node name is ':1648' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ069);
  _EQ069 =  _LC8_A2
         #  _LC3_A2
         #  _LC2_A2
         #  _LC2_A9;

-- Node name is ':1654' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ070);
  _EQ070 = !_LC1_B21 & !_LC1_C20 &  _LC2_A10
         #  _LC1_C20 &  _LC4_A2
         # !_LC1_B21 &  _LC4_A2
         # !_LC2_A10 &  _LC4_A2;

-- Node name is ':1660' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ071);
  _EQ071 =  _LC1_A10 & !_LC1_B21 &  _LC1_C20
         # !_LC1_C20 &  _LC5_A2
         # !_LC1_B21 &  _LC5_A2
         # !_LC1_A10 &  _LC5_A2;

-- Node name is ':1674' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ072);
  _EQ072 =  _LC1_A2 & !_LC1_A9 &  _LC6_A2
         # !_LC1_A9 & !_LC1_A10 &  _LC6_A2;

-- Node name is ':1678' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ073);
  _EQ073 = !_LC1_B21 &  _LC3_A10
         #  _LC1_C20 &  _LC7_A2
         # !_LC1_B21 &  _LC7_A2
         # !_LC3_A10 &  _LC7_A2;

-- Node name is ':1695' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ074);
  _EQ074 = !_LC4_A10 &  _LC6_A6
         #  _LC2_A8 & !_LC4_A10;

-- Node name is '~1702~1' 
-- Equation name is '~1702~1', location is LC1_A3, type is buried.
-- synthesized logic cell 
!_LC1_A3 = _LC1_A3~NOT;
_LC1_A3~NOT = LCELL( _EQ075);
  _EQ075 = !_LC2_A10
         #  _LC1_B21 &  _LC1_C20;

-- Node name is ':1702' 
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = LCELL( _EQ076);
  _EQ076 =  _LC3_A6
         #  _LC2_A2
         #  _LC1_A3;

-- Node name is '~1714~1' 
-- Equation name is '~1714~1', location is LC4_A3, type is buried.
-- synthesized logic cell 
!_LC4_A3 = _LC4_A3~NOT;
_LC4_A3~NOT = LCELL( _EQ077);
  _EQ077 = !_LC1_A10
         #  _LC1_B21 &  _LC1_C20
         # !_LC1_B21 & !_LC1_C20;

-- Node name is ':1714' 
-- Equation name is '_LC5_A6', type is buried 
_LC5_A6  = LCELL( _EQ078);
  _EQ078 = !_LC3_A3 &  _LC4_A6
         #  _LC4_A3
         #  _LC2_A3;

-- Node name is ':1726' 
-- Equation name is '_LC6_A6', type is buried 
_LC6_A6  = LCELL( _EQ079);
  _EQ079 = !_LC1_B21 & !_LC1_C20 &  _LC3_A10
         # !_LC3_A10 &  _LC5_A6
         # !_LC1_B21 & !_LC1_C20 &  _LC5_A6;

-- Node name is '~1738~1' 
-- Equation name is '~1738~1', location is LC2_A8, type is buried.
-- synthesized logic cell 
_LC2_A8  = LCELL( _EQ080);
  _EQ080 = !_LC1_B21 &  _LC1_C20 &  _LC5_A10
         #  _LC4_A8;

-- Node name is ':1750' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ081);
  _EQ081 = !_LC2_A2 &  _LC8_A3
         # !_LC2_A2 &  _LC2_A9
         #  _LC1_A3;

-- Node name is '~1768~1' 
-- Equation name is '~1768~1', location is LC7_A3, type is buried.
-- synthesized logic cell 
_LC7_A3  = LCELL( _EQ082);
  _EQ082 =  _LC1_C20 &  _LC3_A10
         #  _LC1_A10 & !_LC1_C20
         #  _LC1_A10 & !_LC1_B21;

-- Node name is ':1774' 
-- Equation name is '_LC8_A3', type is buried 
_LC8_A3  = LCELL( _EQ083);
  _EQ083 = !_LC3_A3 &  _LC5_A3 & !_LC6_A3
         # !_LC6_A3 &  _LC7_A3;

-- Node name is ':1822' 
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ084);
  _EQ084 =  _LC1_A8 &  _LC3_A8 & !_LC4_A8;

-- Node name is '~1824~1' 
-- Equation name is '~1824~1', location is LC3_A8, type is buried.
-- synthesized logic cell 
_LC3_A8  = LCELL( _EQ085);
  _EQ085 = !_LC1_A12 & !_LC2_A6 & !_LC6_A10;



Project Information      f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,366K