📄 dongtai8duankou.rpt
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Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 20 DFFE + 0 2 0 8 count2 (:50)
- 4 - B 20 DFFE + 0 1 0 9 count1 (:51)
- 1 - B 14 DFFE + 0 0 0 10 count0 (:52)
- 5 - B 20 AND2 0 3 1 0 :370
- 7 - B 20 AND2 0 3 1 4 :792
- 2 - B 15 OR2 2 1 0 1 :795
- 3 - B 20 AND2 0 3 0 5 :802
- 1 - B 15 OR2 1 2 0 1 :805
- 6 - B 20 AND2 0 3 1 4 :812
- 5 - B 14 OR2 1 2 0 1 :815
- 8 - B 20 AND2 0 3 1 4 :822
- 6 - B 14 OR2 1 2 0 1 :825
- 2 - B 14 AND2 0 3 0 5 :832
- 7 - B 14 OR2 1 2 0 1 :835
- 2 - B 20 AND2 0 3 1 4 :842
- 8 - B 14 OR2 1 2 0 1 :845
- 3 - B 14 AND2 0 3 1 4 :852
- 4 - B 14 OR2 1 2 0 5 :855
- 3 - B 24 OR2 2 1 0 1 :861
- 4 - B 24 OR2 1 2 0 1 :864
- 5 - B 24 OR2 1 2 0 1 :867
- 6 - B 24 OR2 1 2 0 1 :870
- 1 - B 24 OR2 1 2 0 1 :873
- 7 - A 10 OR2 1 2 0 1 :876
- 8 - A 10 OR2 1 2 0 5 :879
- 2 - C 20 OR2 2 1 0 1 :885
- 3 - C 20 OR2 1 2 0 1 :888
- 4 - C 20 OR2 1 2 0 1 :891
- 5 - C 20 OR2 1 2 0 1 :894
- 6 - C 20 OR2 1 2 0 1 :897
- 7 - C 20 OR2 1 2 0 1 :900
- 1 - C 20 OR2 1 2 0 22 :903
- 8 - B 24 AND2 1 1 0 1 :913
- 7 - B 24 OR2 2 2 0 1 :914
- 2 - B 24 OR2 1 3 0 1 :915
- 3 - B 21 AND2 1 1 0 1 :922
- 2 - B 21 OR2 1 3 0 1 :923
- 4 - B 21 OR2 1 3 0 1 :924
- 1 - B 21 OR2 1 2 0 21 :927
- 5 - A 10 OR2 s ! 0 2 0 4 ~1315~1
- 4 - A 08 OR2 ! 0 3 0 3 :1315
- 4 - A 10 AND2 0 2 0 4 :1339
- 2 - A 10 OR2 s ! 0 2 0 5 ~1351~1
- 2 - A 02 OR2 ! 0 3 0 6 :1351
- 7 - A 09 OR2 0 4 0 1 :1356
- 3 - A 02 AND2 0 3 0 1 :1363
- 1 - A 10 OR2 s ! 0 2 0 6 ~1399~1
- 3 - A 03 OR2 ! 0 3 0 5 :1399
- 2 - A 06 AND2 s ! 0 3 0 3 ~1426~1
- 2 - A 03 OR2 ! 0 3 0 4 :1435
- 3 - A 10 OR2 s ! 0 2 0 9 ~1447~1
- 8 - A 09 OR2 0 4 0 1 :1452
- 1 - A 02 AND2 s ! 0 2 0 3 ~1471~1
- 3 - A 09 OR2 0 4 1 1 :1486
- 8 - A 06 OR2 0 4 0 1 :1506
- 7 - A 06 OR2 s 0 2 0 1 ~1513~1
- 1 - A 09 OR2 s ! 0 4 0 3 ~1534~1
- 1 - A 12 OR2 s ! 0 4 0 2 ~1534~2
- 6 - A 03 OR2 s ! 0 2 0 1 ~1534~3
- 1 - A 06 OR2 0 4 1 1 :1534
- 4 - A 09 OR2 0 3 0 1 :1546
- 6 - A 09 OR2 0 4 0 1 :1573
- 5 - A 09 OR2 0 4 1 1 :1582
- 6 - A 10 OR2 s ! 0 4 0 2 ~1597~1
- 6 - A 08 OR2 0 3 0 1 :1597
- 7 - A 08 OR2 0 4 0 1 :1606
- 8 - A 08 OR2 0 4 0 1 :1623
- 5 - A 08 OR2 0 4 1 1 :1630
- 2 - A 09 OR2 s 0 2 0 2 ~1648~1
- 4 - A 02 OR2 0 4 0 1 :1648
- 5 - A 02 OR2 0 4 0 1 :1654
- 6 - A 02 OR2 0 4 0 1 :1660
- 7 - A 02 OR2 0 4 0 1 :1674
- 8 - A 02 OR2 0 4 1 1 :1678
- 3 - A 06 OR2 0 3 0 1 :1695
- 1 - A 03 OR2 s ! 0 3 0 4 ~1702~1
- 4 - A 06 OR2 0 3 0 1 :1702
- 4 - A 03 OR2 s ! 0 3 0 4 ~1714~1
- 5 - A 06 OR2 0 4 0 1 :1714
- 6 - A 06 OR2 0 4 1 1 :1726
- 2 - A 08 OR2 s 0 4 0 5 ~1738~1
- 5 - A 03 OR2 0 4 0 1 :1750
- 7 - A 03 OR2 s 0 4 0 1 ~1768~1
- 8 - A 03 OR2 0 4 1 1 :1774
- 1 - A 08 AND2 0 2 1 0 :1822
- 3 - A 08 AND2 s 0 3 0 1 ~1824~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 16/ 96( 16%) 16/ 48( 33%) 0/ 48( 0%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 13/ 96( 13%) 0/ 48( 0%) 17/ 48( 35%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
C: 10/ 96( 10%) 0/ 48( 0%) 5/ 48( 10%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** EQUATIONS **
clk : INPUT;
p10 : INPUT;
p11 : INPUT;
p12 : INPUT;
p13 : INPUT;
p20 : INPUT;
p21 : INPUT;
p22 : INPUT;
p23 : INPUT;
p30 : INPUT;
p31 : INPUT;
p32 : INPUT;
p33 : INPUT;
p40 : INPUT;
p41 : INPUT;
p42 : INPUT;
p43 : INPUT;
p50 : INPUT;
p51 : INPUT;
p52 : INPUT;
p53 : INPUT;
p60 : INPUT;
p61 : INPUT;
p62 : INPUT;
p63 : INPUT;
p70 : INPUT;
p71 : INPUT;
p72 : INPUT;
p73 : INPUT;
p80 : INPUT;
p81 : INPUT;
p82 : INPUT;
p83 : INPUT;
-- Node name is ':52' = 'count0'
-- Equation name is 'count0', location is LC1_B14, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':51' = 'count1'
-- Equation name is 'count1', location is LC4_B20, type is buried.
count1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & !count1
# !count0 & count1;
-- Node name is ':50' = 'count2'
-- Equation name is 'count2', location is LC1_B20, type is buried.
count2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count0 & count2
# !count1 & count2
# count0 & count1 & !count2;
-- Node name is 'duan0'
-- Equation name is 'duan0', type is output
duan0 = _LC1_A8;
-- Node name is 'duan1'
-- Equation name is 'duan1', type is output
duan1 = _LC8_A3;
-- Node name is 'duan2'
-- Equation name is 'duan2', type is output
duan2 = _LC6_A6;
-- Node name is 'duan3'
-- Equation name is 'duan3', type is output
duan3 = _LC8_A2;
-- Node name is 'duan4'
-- Equation name is 'duan4', type is output
duan4 = _LC5_A8;
-- Node name is 'duan5'
-- Equation name is 'duan5', type is output
duan5 = _LC5_A9;
-- Node name is 'duan6'
-- Equation name is 'duan6', type is output
duan6 = _LC1_A6;
-- Node name is 'duan7'
-- Equation name is 'duan7', type is output
duan7 = _LC3_A9;
-- Node name is 'wei0'
-- Equation name is 'wei0', type is output
wei0 = _LC3_B14;
-- Node name is 'wei1'
-- Equation name is 'wei1', type is output
wei1 = _LC2_B20;
-- Node name is 'wei2'
-- Equation name is 'wei2', type is output
wei2 = GND;
-- Node name is 'wei3'
-- Equation name is 'wei3', type is output
wei3 = _LC8_B20;
-- Node name is 'wei4'
-- Equation name is 'wei4', type is output
wei4 = _LC6_B20;
-- Node name is 'wei5'
-- Equation name is 'wei5', type is output
wei5 = GND;
-- Node name is 'wei6'
-- Equation name is 'wei6', type is output
wei6 = _LC7_B20;
-- Node name is 'wei7'
-- Equation name is 'wei7', type is output
wei7 = _LC5_B20;
-- Node name is ':370'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = LCELL( _EQ003);
_EQ003 = count0 & count1 & count2;
-- Node name is ':792'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = LCELL( _EQ004);
_EQ004 = !count0 & count1 & count2;
-- Node name is ':795'
-- Equation name is '_LC2_B15', type is buried
_LC2_B15 = LCELL( _EQ005);
_EQ005 = !_LC7_B20 & p83
# _LC7_B20 & p73;
-- Node name is ':802'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ006);
_EQ006 = count0 & !count1 & count2;
-- Node name is ':805'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = LCELL( _EQ007);
_EQ007 = _LC2_B15 & !_LC3_B20
# _LC3_B20 & p63;
-- Node name is ':812'
-- Equation name is '_LC6_B20', type is buried
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