📄 dongtai8duankou.rpt
字号:
Project Information f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/31/2006 10:30:34
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DONGTAI8DUANKOU
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
dongtai8duankou
EPF10K10LC84-3 33 16 0 0 0 % 86 14 %
User Pins: 33 16 0
Project Information f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
** FILE HIERARCHY **
|lpm_add_sub:66|
|lpm_add_sub:66|addcore:adder|
|lpm_add_sub:66|altshift:result_ext_latency_ffs|
|lpm_add_sub:66|altshift:carry_ext_latency_ffs|
|lpm_add_sub:66|altshift:oflow_ext_latency_ffs|
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
***** Logic for device 'dongtai8duankou' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** ERROR SUMMARY **
Info: Chip 'dongtai8duankou' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
R R R R R R R O
E E E E E E E N
S S S S S S V S G F
E E E E E d E C E N _ ^
R R R R R u R C R D # D n
V V V V V a V I V p c p p I p p p p T O C
E E E E E n E N E 8 l 5 3 N 5 1 8 7 C N E
D D D D D 1 D T D 3 k 3 2 T 2 3 0 0 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | duan6
^nCE | 14 72 | p22
#TDI | 15 71 | p12
duan0 | 16 70 | duan5
duan7 | 17 69 | duan3
duan4 | 18 68 | GNDINT
duan2 | 19 67 | p20
VCCINT | 20 66 | p72
p60 | 21 65 | wei7
p23 | 22 EPF10K10LC84-3 64 | p50
p82 | 23 63 | VCCINT
p33 | 24 62 | p21
p40 | 25 61 | p51
GNDINT | 26 60 | p31
p81 | 27 59 | p11
wei1 | 28 58 | wei4
p41 | 29 57 | #TMS
p71 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | p30
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R w R w V G p p p V G w p p p p w w
C n E E e E e C N 7 4 6 C N e 6 1 4 6 e e
C C S S i S i C D 3 3 3 C D i 2 0 2 1 i i
I O E E 5 E 2 I I I I 0 3 6
N N R R R N N N N
T F V V V T T T T
I E E E
G D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A3 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
A6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
A10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B14 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
B15 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
B20 8/ 8(100%) 5/ 8( 62%) 8/ 8(100%) 1/2 0/2 1/22( 4%)
B21 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
B24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
C20 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 43/53 ( 81%)
Total logic cells used: 86/576 ( 14%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.16/4 ( 79%)
Total fan-in: 272/2304 ( 11%)
Total input pins required: 33
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 86
Total flipflops required: 3
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 17/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 8 8 0 0 8 0 8 8 8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 49/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 2 0 0 0 0 8 4 0 0 8 30/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 7/0
Total: 0 8 8 0 0 8 0 8 8 8 0 1 0 0 8 2 0 0 0 0 15 4 0 0 8 86/0
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
49 - - - 16 INPUT 0 0 0 1 p10
59 - - C -- INPUT 0 0 0 1 p11
71 - - A -- INPUT 0 0 0 1 p12
80 - - - 23 INPUT 0 0 0 1 p13
67 - - B -- INPUT 0 0 0 1 p20
62 - - C -- INPUT 0 0 0 1 p21
72 - - A -- INPUT 0 0 0 1 p22
22 - - B -- INPUT 0 0 0 1 p23
54 - - - 21 INPUT 0 0 0 1 p30
60 - - C -- INPUT 0 0 0 1 p31
83 - - - 13 INPUT 0 0 0 1 p32
24 - - B -- INPUT 0 0 0 1 p33
25 - - B -- INPUT 0 0 0 1 p40
29 - - C -- INPUT 0 0 0 1 p41
50 - - - 17 INPUT 0 0 0 1 p42
43 - - - -- INPUT 0 0 0 1 p43
64 - - B -- INPUT 0 0 0 1 p50
61 - - C -- INPUT 0 0 0 1 p51
81 - - - 22 INPUT 0 0 0 1 p52
84 - - - -- INPUT 0 0 0 1 p53
21 - - B -- INPUT 0 0 0 1 p60
51 - - - 18 INPUT 0 0 0 1 p61
48 - - - 15 INPUT 0 0 0 1 p62
44 - - - -- INPUT 0 0 0 1 p63
78 - - - 24 INPUT 0 0 0 1 p70
30 - - C -- INPUT 0 0 0 1 p71
66 - - B -- INPUT 0 0 0 1 p72
42 - - - -- INPUT 0 0 0 1 p73
79 - - - 24 INPUT 0 0 0 1 p80
27 - - C -- INPUT 0 0 0 1 p81
23 - - B -- INPUT 0 0 0 1 p82
2 - - - -- INPUT 0 0 0 1 p83
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:f:\zhangshuhua\eda_shiyan_zsh\plj\dongtai8duankou.rpt
dongtai8duankou
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
16 - - A -- OUTPUT 0 1 0 0 duan0
6 - - - 04 OUTPUT 0 1 0 0 duan1
19 - - A -- OUTPUT 0 1 0 0 duan2
69 - - A -- OUTPUT 0 1 0 0 duan3
18 - - A -- OUTPUT 0 1 0 0 duan4
70 - - A -- OUTPUT 0 1 0 0 duan5
73 - - A -- OUTPUT 0 1 0 0 duan6
17 - - A -- OUTPUT 0 1 0 0 duan7
47 - - - 14 OUTPUT 0 1 0 0 wei0
28 - - C -- OUTPUT 0 1 0 0 wei1
39 - - - 11 OUTPUT 0 0 0 0 wei2
52 - - - 19 OUTPUT 0 1 0 0 wei3
58 - - C -- OUTPUT 0 1 0 0 wei4
37 - - - 09 OUTPUT 0 0 0 0 wei5
53 - - - 20 OUTPUT 0 1 0 0 wei6
65 - - B -- OUTPUT 0 1 0 0 wei7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -