📄 pljl.rpt
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- 6 - B 02 OR2 s ! 0 2 0 5 |DONGTAI8DUANKOU:17|~1351~1
- 2 - A 02 OR2 ! 0 3 0 6 |DONGTAI8DUANKOU:17|:1351
- 7 - A 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1356
- 3 - B 03 AND2 0 3 0 1 |DONGTAI8DUANKOU:17|:1363
- 1 - B 02 OR2 s ! 0 2 0 6 |DONGTAI8DUANKOU:17|~1399~1
- 5 - A 04 OR2 ! 0 3 0 5 |DONGTAI8DUANKOU:17|:1399
- 3 - A 04 AND2 s ! 0 3 0 3 |DONGTAI8DUANKOU:17|~1426~1
- 8 - A 04 OR2 ! 0 3 0 4 |DONGTAI8DUANKOU:17|:1435
- 4 - B 02 OR2 s ! 0 2 0 9 |DONGTAI8DUANKOU:17|~1447~1
- 8 - A 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1452
- 1 - B 03 OR2 s 0 2 0 1 |DONGTAI8DUANKOU:17|~1471~1
- 1 - A 03 OR2 0 4 1 1 |DONGTAI8DUANKOU:17|:1486
- 7 - A 01 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1498
- 8 - A 01 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1513
- 4 - A 03 OR2 s ! 0 4 0 3 |DONGTAI8DUANKOU:17|~1534~1
- 3 - A 01 OR2 s ! 0 4 0 2 |DONGTAI8DUANKOU:17|~1534~2
- 3 - A 03 OR2 s ! 0 2 0 1 |DONGTAI8DUANKOU:17|~1534~3
- 2 - A 01 OR2 0 3 1 1 |DONGTAI8DUANKOU:17|:1534
- 4 - A 01 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1546
- 5 - A 01 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1573
- 6 - A 01 OR2 0 4 1 1 |DONGTAI8DUANKOU:17|:1582
- 2 - B 02 OR2 s ! 0 4 0 2 |DONGTAI8DUANKOU:17|~1597~1
- 4 - A 02 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1597
- 6 - A 02 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1606
- 7 - A 02 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1623
- 1 - A 02 OR2 0 4 1 1 |DONGTAI8DUANKOU:17|:1630
- 4 - B 03 OR2 s 0 3 0 2 |DONGTAI8DUANKOU:17|~1648~1
- 5 - B 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1648
- 6 - B 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1654
- 7 - B 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1660
- 8 - B 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1674
- 2 - B 03 OR2 0 4 1 1 |DONGTAI8DUANKOU:17|:1678
- 4 - A 04 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1695
- 5 - A 02 OR2 s ! 0 3 0 4 |DONGTAI8DUANKOU:17|~1702~1
- 6 - A 04 OR2 0 3 0 1 |DONGTAI8DUANKOU:17|:1702
- 1 - A 04 OR2 s ! 0 3 0 4 |DONGTAI8DUANKOU:17|~1714~1
- 7 - A 04 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1714
- 2 - A 04 OR2 0 4 1 1 |DONGTAI8DUANKOU:17|:1726
- 2 - A 03 OR2 0 4 0 1 |DONGTAI8DUANKOU:17|:1750
- 5 - A 03 OR2 s 0 4 0 1 |DONGTAI8DUANKOU:17|~1768~1
- 6 - A 03 OR2 0 4 1 1 |DONGTAI8DUANKOU:17|:1774
- 1 - A 05 OR2 0 3 1 0 |DONGTAI8DUANKOU:17|:1822
- 1 - A 01 AND2 s 0 3 0 1 |DONGTAI8DUANKOU:17|~1824~1
- 3 - C 18 DFFE 0 2 0 1 |REG32B:3|:34
- 3 - C 16 DFFE 0 2 0 1 |REG32B:3|:36
- 6 - C 18 DFFE 0 2 0 1 |REG32B:3|:38
- 3 - C 20 DFFE 0 2 0 1 |REG32B:3|:40
- 4 - C 18 DFFE 0 2 0 1 |REG32B:3|:42
- 4 - C 16 DFFE 0 2 0 1 |REG32B:3|:44
- 7 - C 18 DFFE 0 2 0 1 |REG32B:3|:46
- 4 - C 20 DFFE 0 2 0 1 |REG32B:3|:48
- 8 - C 21 DFFE 0 2 0 1 |REG32B:3|:50
- 2 - C 16 DFFE 0 2 0 1 |REG32B:3|:52
- 5 - C 18 DFFE 0 2 0 1 |REG32B:3|:54
- 2 - C 20 DFFE 0 2 0 1 |REG32B:3|:56
- 2 - C 19 DFFE 0 2 0 1 |REG32B:3|:58
- 7 - C 16 DFFE 0 2 0 1 |REG32B:3|:60
- 2 - B 17 DFFE 0 2 0 1 |REG32B:3|:62
- 7 - C 20 DFFE 0 2 0 1 |REG32B:3|:64
- 3 - B 24 DFFE 0 2 0 1 |REG32B:3|:66
- 2 - B 13 DFFE 0 2 0 1 |REG32B:3|:68
- 4 - B 17 DFFE 0 2 0 1 |REG32B:3|:70
- 2 - B 20 DFFE 0 2 0 1 |REG32B:3|:72
- 5 - B 24 DFFE 0 2 0 1 |REG32B:3|:74
- 1 - B 15 DFFE 0 2 0 1 |REG32B:3|:76
- 2 - B 16 DFFE 0 2 0 1 |REG32B:3|:78
- 4 - B 20 DFFE 0 2 0 1 |REG32B:3|:80
- 7 - B 24 DFFE 0 2 0 1 |REG32B:3|:82
- 8 - B 24 DFFE 0 2 0 1 |REG32B:3|:84
- 4 - B 16 DFFE 0 2 0 1 |REG32B:3|:86
- 6 - B 20 DFFE 0 2 0 1 |REG32B:3|:88
- 5 - B 02 DFFE 0 2 0 1 |REG32B:3|:90
- 1 - B 11 DFFE 0 2 0 1 |REG32B:3|:92
- 2 - B 09 DFFE 0 2 0 1 |REG32B:3|:94
- 8 - B 20 DFFE 0 2 0 1 |REG32B:3|:96
- 6 - C 06 DFFE 0 1 0 66 |TESTCTL:4|div2clk (|TESTCTL:4|:5)
- 4 - C 06 OR2 ! 0 2 0 32 |TESTCTL:4|:36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
pljl
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 12/ 48( 25%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 15/ 96( 15%) 11/ 48( 22%) 20/ 48( 41%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 7/ 96( 7%) 8/ 48( 16%) 22/ 48( 45%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
pljl
** CLOCK SIGNALS **
Type Fan-out Name
DFF 67 |TESTCTL:4|div2clk
INPUT 14 clk
LCELL 12 |CLKGEN:18|:374
LCELL 4 |CNT10:1|:173
LCELL 4 |CNT10:5|:173
LCELL 4 |CNT10:6|:173
LCELL 4 |CNT10:8|:173
LCELL 4 |CNT10:10|:173
LCELL 4 |CNT10:11|:173
INPUT 4 fin
LCELL 4 |CNT10:7|:173
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
pljl
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 32 |TESTCTL:4|:36
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
pljl
** EQUATIONS **
clk : INPUT;
fin : INPUT;
-- Node name is 'duani0'
-- Equation name is 'duani0', type is output
duani0 = _LC1_A5;
-- Node name is 'duani1'
-- Equation name is 'duani1', type is output
duani1 = _LC6_A3;
-- Node name is 'duani2'
-- Equation name is 'duani2', type is output
duani2 = _LC2_A4;
-- Node name is 'duani3'
-- Equation name is 'duani3', type is output
duani3 = _LC2_B3;
-- Node name is 'duani4'
-- Equation name is 'duani4', type is output
duani4 = _LC1_A2;
-- Node name is 'duani5'
-- Equation name is 'duani5', type is output
duani5 = _LC6_A1;
-- Node name is 'duani6'
-- Equation name is 'duani6', type is output
duani6 = _LC2_A1;
-- Node name is 'duani7'
-- Equation name is 'duani7', type is output
duani7 = _LC1_A3;
-- Node name is 'wei0'
-- Equation name is 'wei0', type is output
wei0 = _LC3_C21;
-- Node name is 'wei1'
-- Equation name is 'wei1', type is output
wei1 = _LC1_C21;
-- Node name is 'wei2'
-- Equation name is 'wei2', type is output
wei2 = _LC2_C24;
-- Node name is 'wei3'
-- Equation name is 'wei3', type is output
wei3 = _LC1_C24;
-- Node name is 'wei4'
-- Equation name is 'wei4', type is output
wei4 = _LC4_C24;
-- Node name is 'wei5'
-- Equation name is 'wei5', type is output
wei5 = _LC7_C21;
-- Node name is 'wei6'
-- Equation name is 'wei6', type is output
wei6 = _LC4_C13;
-- Node name is 'wei7'
-- Equation name is 'wei7', type is output
wei7 = _LC4_C11;
-- Node name is '|CLKGEN:18|:13' = '|CLKGEN:18|cnter0'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC3_C8 & !_LC5_C6
# !_LC2_C8 & !_LC5_C6
# !_LC2_C10 & !_LC5_C6;
-- Node name is '|CLKGEN:18|:12' = '|CLKGEN:18|cnter1'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC2_C6 & !_LC3_C6 & _LC5_C6
# !_LC2_C6 & _LC3_C6 & !_LC5_C6;
-- Node name is '|CLKGEN:18|:11' = '|CLKGEN:18|cnter2'
-- Equation name is '_LC7_C10', type is buried
_LC7_C10 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_C6 & !_LC2_C6 & _LC7_C10
# _LC1_C6 & !_LC2_C6 & !_LC7_C10;
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