📄 pljl.rpt
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Project Information f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 11/03/2006 08:41:32
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
pljl EPF10K10LC84-4 2 16 0 0 0 % 202 35 %
User Pins: 2 16 0
Project Information f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
pljl@1 clk
pljl@5 duani0
pljl@6 duani1
pljl@7 duani2
pljl@8 duani3
pljl@9 duani4
pljl@10 duani5
pljl@11 duani6
pljl@16 duani7
pljl@43 fin
pljl@72 wei0
pljl@73 wei1
pljl@78 wei2
pljl@79 wei3
pljl@80 wei4
pljl@81 wei5
pljl@83 wei6
pljl@3 wei7
Project Information f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
** FILE HIERARCHY **
|cnt10:7|
|cnt10:7|lpm_add_sub:73|
|cnt10:7|lpm_add_sub:73|addcore:adder|
|cnt10:7|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:7|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:7|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:12|
|cnt10:12|lpm_add_sub:73|
|cnt10:12|lpm_add_sub:73|addcore:adder|
|cnt10:12|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:12|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:12|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:6|
|cnt10:6|lpm_add_sub:73|
|cnt10:6|lpm_add_sub:73|addcore:adder|
|cnt10:6|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:6|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:6|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:10|
|cnt10:10|lpm_add_sub:73|
|cnt10:10|lpm_add_sub:73|addcore:adder|
|cnt10:10|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:10|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:10|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:5|
|cnt10:5|lpm_add_sub:73|
|cnt10:5|lpm_add_sub:73|addcore:adder|
|cnt10:5|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:5|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:5|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:11|
|cnt10:11|lpm_add_sub:73|
|cnt10:11|lpm_add_sub:73|addcore:adder|
|cnt10:11|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:11|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:11|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:1|
|cnt10:1|lpm_add_sub:73|
|cnt10:1|lpm_add_sub:73|addcore:adder|
|cnt10:1|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:1|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:1|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:8|
|cnt10:8|lpm_add_sub:73|
|cnt10:8|lpm_add_sub:73|addcore:adder|
|cnt10:8|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:8|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:8|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|reg32b:3|
|testctl:4|
|dongtai8duankou:17|
|dongtai8duankou:17|lpm_add_sub:66|
|dongtai8duankou:17|lpm_add_sub:66|addcore:adder|
|dongtai8duankou:17|lpm_add_sub:66|altshift:result_ext_latency_ffs|
|dongtai8duankou:17|lpm_add_sub:66|altshift:carry_ext_latency_ffs|
|dongtai8duankou:17|lpm_add_sub:66|altshift:oflow_ext_latency_ffs|
|clkgen:18|
|clkgen:18|lpm_add_sub:138|
|clkgen:18|lpm_add_sub:138|addcore:adder|
|clkgen:18|lpm_add_sub:138|altshift:result_ext_latency_ffs|
|clkgen:18|lpm_add_sub:138|altshift:carry_ext_latency_ffs|
|clkgen:18|lpm_add_sub:138|altshift:oflow_ext_latency_ffs|
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
pljl
***** Logic for device 'pljl' compiled without errors.
Device: EPF10K10LC84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
O
N
d d d d d d d V G G G F
u u u u u u u C N N N _ ^
a a a a a a a C w D D w D w w w w # D n
n n n n n n n I e I c I e I e e e e T O C
i i i i i i i N i N l N i N i i i i C N E
6 5 4 3 2 1 0 T 7 T k T 6 T 5 4 3 2 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | wei1
^nCE | 14 72 | wei0
#TDI | 15 71 | RESERVED
duani7 | 16 70 | RESERVED
RESERVED | 17 69 | RESERVED
RESERVED | 18 68 | GNDINT
RESERVED | 19 67 | RESERVED
VCCINT | 20 66 | RESERVED
RESERVED | 21 65 | RESERVED
RESERVED | 22 EPF10K10LC84-4 64 | RESERVED
RESERVED | 23 63 | VCCINT
RESERVED | 24 62 | RESERVED
RESERVED | 25 61 | RESERVED
GNDINT | 26 60 | RESERVED
RESERVED | 27 59 | RESERVED
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G f G V G R R R R R R R
C n E E E E E C N N i N C N E E E E E E E
C C S S S S S C D D n D C D S S S S S S S
I O E E E E E I I I I I I E E E E E E E
N N R R R R R N N N N N N R R R R R R R
T F V V V V V T T T T T T V V V V V V V
I E E E E E E E E E E E E
G D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\zhangshuhua\keneishiyan\shiyan10\pljl.rpt
pljl
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
A2 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A3 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A4 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
A5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B2 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
B3 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
B6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 2/22( 9%)
B9 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B13 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
B15 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B16 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B17 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
B20 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
B21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
B24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
C6 6/ 8( 75%) 2/ 8( 25%) 5/ 8( 62%) 2/2 0/2 3/22( 13%)
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