match_rec.srs

使用VERILOG实现QPSK信号的匹配滤波

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@ 
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7, Build 192R from Synplicity, Inc.
# Copyright 1994-2007 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jun 06 16:59:57 2008
#
#
#OPTIONS:"|-top|match_rec|-primux|-dspmac|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-autosm|-I|E:\\wangqiuju\\study\\researchproject\\FPGA\\book_onFPGA\\wireless-FPGA-design-code\\Verilog-code\\c12_0\\12-2_0\\match_rec\\|-I|D:\\Program\\FPGA_software\\Synplicity\\fpga_8804\\lib|-v2001|-devicelib|D:\\Program\\FPGA_software\\Synplicity\\fpga_8804\\lib\\xilinx\\unisim.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"D:\\Program\\FPGA_software\\Synplicity\\fpga_8804\\bin\\c_ver.exe":1176279206
#CUR:"D:\\Program\\FPGA_software\\Synplicity\\fpga_8804\\lib\\xilinx\\unisim.v":1178603006
#CUR:"E:\\wangqiuju\\study\\researchproject\\FPGA\\book_onFPGA\\wireless-FPGA-design-code\\Verilog-code\\c12_0\\12-2_0\\match_rec\\match_rec.v":1212742711
f "D:\Program\FPGA_software\Synplicity\fpga_8804\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v"; # file 1
af .is_verilog 1;
@E
@ 
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