test_match_rec.v

使用VERILOG实现QPSK信号的匹配滤波

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:05:53 06/06/2008
// Design Name:   match_rec
// Module Name:   E:/wangqiuju/study/researchproject/FPGA/book_onFPGA/wireless-FPGA-design-code/Verilog-code/c12_0/12-2_0/match_rec/test_match_rec.v
// Project Name:  match_rec
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: match_rec
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_match_rec;

	// Inputs
	reg clk;
	reg reset;
	reg x_in;

	// Outputs
	wire [1:0] y_out;

	// Instantiate the Unit Under Test (UUT)
	match_rec uut (
		.clk(clk), 
		.reset(reset), 
		.x_in(x_in), 
		.y_out(y_out)
	);
   always #50 clk=~clk;
	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		x_in = 0;

		// Wait 100 ns for global reset to finish
		#150;
        
		// Add stimulus here
	
		reset=1;
		x_in=1;
		#200 x_in=0;
		#200 x_in=1;
		#100 x_in=0;
		#200 x_in=1;
		#100 x_in=0;
		#100 x_in=1;
		#200 x_in=0;
		#100 $stop;

	end
      
endmodule