match_rec.prj

使用VERILOG实现QPSK信号的匹配滤波

#
##-- Synplicity, Inc.
##-- Project file E:/wangqiuju/study/researchproject/FPGA/book_onFPGA/wireless-FPGA-design-code/Verilog-code/c12_0/12-2_0/match_rec/match_rec.prj.
##-- Generated using ISE.

#implementation: match_rec
impl -add "match_rec"

##device options
proc findmatch {spec args} {  set _Arglist [join $args " "];  set _Idx [lsearch -glob $_Arglist $spec];  if {$_Idx != -1} {  return [lindex $_Arglist $_Idx];  } else {  return $spec;  }  }
         
proc findpackage {spec} { findmatch $spec [partdata -package [part]]}
proc findgrade   {spec} { findmatch $spec [partdata -grade   [part]]}
set_option -technology VIRTEX4
set_option -part xc4vsx35
set_option -package [findpackage {ff668}]
set_option -speed_grade [findgrade {-10}]

## Libraries

## Source files
add_file {match_rec.v}

## Additional _Compile options
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -default_enum_encoding default
set_option -top_module match_rec
set_option -use_fsm_explorer 0

## Additional _Map options
set_option -frequency auto
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -modular 0
set_option -retiming 0

## Additional _Simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

## Additional _PlaceAndRoute options
set_option -write_apr_constraint 1

## Additional _ImplAttr options
set_option -num_critical_paths 0
set_option -num_startend_points 0

set_option -vlog_std v2001
set_option -compiler_compatible 0

##--Set result format/file last
project -result_file {E:/wangqiuju/study/researchproject/FPGA/book_onFPGA/wireless-FPGA-design-code/Verilog-code/c12_0/12-2_0/match_rec/match_rec.edn}

##-- p_Constraint file
add_file -constraint {E:/wangqiuju/study/researchproject/FPGA/book_onFPGA/wireless-FPGA-design-code/Verilog-code/c12_0/12-2_0/match_rec/match_rec.sdc}