match_rec.v

使用VERILOG实现QPSK信号的匹配滤波

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:18:04 06/06/2008 
// Design Name: 
// Module Name:    match_rec 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module match_rec(clk,reset,x_in,y_out);
	 input clk ;         //接收机工作时钟
    input reset;
    input x_in;        //输入信号，比特流
    output [1:0] y_out;  //输出信号，波形编号
	 
	 reg[1:0] y_out;
	 reg[1:0] cnt;
	 reg[2:0] cnt1,cnt2,cnt3,cnt4;    //各个匹配滤波器的权重因子
	 
	 always @(posedge clk) begin
	 if(!reset) begin    //初始化变量
	 cnt<=0;
	 cnt1<=0;
	 cnt2<=0;
	 cnt3<=0;
	 cnt4<=0;
	 y_out<=0;
	 end
	 else begin
	 case(cnt)      //完成状态机的运算
	    2'b00:begin
		     if(x_in==1) begin
			   cnt1<=1;
				cnt2<=1;
				cnt3<=0;
				cnt4<=0;
			  end
			  else begin 
			   cnt1<=0;
				cnt2<=0;
				cnt3<=1;
				cnt4<=1;
			  end
			  //if(cnt1>2)
			  // y_out<=0;
			  //else if(cnt2>2)
			  //  y_out<=1;
			  //else if(cnt3>2)
			  //  y_out<=2;
			  //else
			  //  y_out<=3;
		     end
		 2'b01:begin
		     if(x_in==1) begin
			   cnt1<=cnt1+1;
				cnt2<=cnt2;
				cnt3<=cnt3;
				cnt4<=cnt4+1;
			  end
			  else begin 
			   cnt1<=cnt1;
				cnt2<=cnt2+1;
				cnt3<=cnt3+1;
				cnt4<=cnt4;
			  end
			 end
		  2'b10:begin
		     if(x_in==1) begin
			   cnt1<=cnt1;
				cnt2<=cnt2;
				cnt3<=cnt3+1;
				cnt4<=cnt4+1;
			  end
			  else begin 
			   cnt1<=cnt1+1;
				cnt2<=cnt2+1;
				cnt3<=cnt3;
				cnt4<=cnt4;
			  end
			 end
		  2'b11:begin
		     if(x_in==1) begin
			   cnt1<=cnt1;
				cnt2<=cnt2+1;
				cnt3<=cnt3+1;
				cnt4<=cnt4;
			  end
			  else begin 
			   cnt1<=cnt1+1;
				cnt2<=cnt2;
				cnt3<=cnt3;
				cnt4<=cnt4+1;
			  end
			 end
	 endcase
	   cnt=cnt+1;  //计数器计数
		if(cnt==0) begin
		if(cnt1>2)
			    y_out<=0;
			  else if(cnt2>2)
			    y_out<=1;
			  else if(cnt3>2)
			    y_out<=2;
			  else
			    y_out<=3;
		   end
		end

	 end


endmodule