run_options.txt

使用VERILOG实现QPSK信号的匹配滤波

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.8.0.4
#-- Project file E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\run_options.txt
#-- Written on Fri Jun 06 16:59:55 2008


#add_file options
add_file -verilog "match_rec.v"
add_file -constraint "E:/wangqiuju/study/researchproject/FPGA/book_onFPGA/wireless-FPGA-design-code/Verilog-code/c12_0/12-2_0/match_rec/match_rec.sdc"


#implementation: "match_rec"
impl -add match_rec -type fpga

#device options
set_option -technology VIRTEX4
set_option -part xc4vsx35
set_option -package ff668
set_option -speed_grade -10
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "match_rec"

#map options
set_option -frequency auto
set_option -run_prop_extract 1
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./match_rec.edn"

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 0
set_option -num_startend_points 0
impl -active "match_rec"