match_rec.srd

使用VERILOG实现QPSK信号的匹配滤波

f "noname"; #file 0
f "d:\program\fpga_software\synplicity\fpga_8804\lib\xilinx\unisim.v"; #file 1
f "e:\wangqiuju\study\researchproject\fpga\book_onfpga\wireless-fpga-design-code\verilog-code\c12_0\12-2_0\match_rec\match_rec.v"; #file 2
VNAME 'work.match_rec.verilog'; # view id 0
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