📄 match_rec_srr.htm
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<!@TC:1212742801>
#Build: Synplify Pro 8.8.0.4, Build 008R, Dec 7 2006
#install: D:\Program\FPGA_software\Synplicity\fpga_8804
#OS: Windows XP 5.1
#Hostname: USER-73B7470377
#Implementation: match_rec
#Fri Jun 06 16:59:55 2008
<a name=compilerReport1>$ Start of Compile
#Fri Jun 06 16:59:55 2008
Synplicity Verilog Compiler, version 3.7, Build 192R, built Apr 11 2007
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
@I::"D:\Program\FPGA_software\Synplicity\fpga_8804\lib\xilinx\unisim.v"
@I::"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v"
Verilog syntax check successful!
Selecting top level module match_rec
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:21:7:21:16:@N:CG364:@XP_MSG">match_rec.v(21)</a><!@TM:1212742801> | Synthesizing module match_rec
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:67:10:67:14:@N:CG179:@XP_MSG">match_rec.v(67)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:68:10:68:14:@N:CG179:@XP_MSG">match_rec.v(68)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:72:12:72:16:@N:CG179:@XP_MSG">match_rec.v(72)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:75:10:75:14:@N:CG179:@XP_MSG">match_rec.v(75)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:80:12:80:16:@N:CG179:@XP_MSG">match_rec.v(80)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:81:10:81:14:@N:CG179:@XP_MSG">match_rec.v(81)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:88:10:88:14:@N:CG179:@XP_MSG">match_rec.v(88)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:89:10:89:14:@N:CG179:@XP_MSG">match_rec.v(89)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:94:12:94:16:@N:CG179:@XP_MSG">match_rec.v(94)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:97:10:97:14:@N:CG179:@XP_MSG">match_rec.v(97)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:101:10:101:14:@N:CG179:@XP_MSG">match_rec.v(101)</a><!@TM:1212742801> | Removing redundant assignment
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:102:10:102:14:@N:CG179:@XP_MSG">match_rec.v(102)</a><!@TM:1212742801> | Removing redundant assignment
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v:31:2:31:8:@W:CL169:@XP_MSG">match_rec.v(31)</a><!@TM:1212742801> | Pruning Register cnt4[2:0] </font>
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 06 16:59:57 2008
###########################################################]
<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.8.0p, Build 069R, Built Apr 17 2007 19:41:05
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
Product Version Version 8.8.0.4
Reading constraint file: E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.sdc
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1212742801> | Running in 32-bit mode.
@N:<a href="@N:MF257:@XP_HELP">MF257</a> : <!@TM:1212742801> | Gated clock conversion enabled
Reading Xilinx I/O pad type table from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/gttype.txt>
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1212742801> | Autoconstrain Mode is ON
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 45MB)
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 45MB)
######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[
================================================================
Instance:Pin Generated Clock Optimization Status
================================================================
######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 45MB)
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 46MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 46MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s 0.00ns 22 / 13
2 0h:00m:00s 0.00ns 22 / 13
3 0h:00m:00s 0.00ns 22 / 13
------------------------------------------------------------
Timing driven replication report
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="e:\wangqiuju\study\researchproject\fpga\book_onfpga\wireless-fpga-design-code\verilog-code\c12_0\12-2_0\match_rec\match_rec.v:31:2:31:8:@N:FX271:@XP_MSG">match_rec.v(31)</a><!@TM:1212742801> | Instance "cnt[1]" with 9 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="e:\wangqiuju\study\researchproject\fpga\book_onfpga\wireless-fpga-design-code\verilog-code\c12_0\12-2_0\match_rec\match_rec.v:31:2:31:8:@N:FX271:@XP_MSG">match_rec.v(31)</a><!@TM:1212742801> | Instance "cnt[0]" with 9 loads has been replicated 1 time(s) to improve timing
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.76ns 24 / 15
2 0h:00m:00s -0.76ns 24 / 15
3 0h:00m:00s -0.76ns 24 / 15
Timing driven replication report
No replication required.
4 0h:00m:00s -0.76ns 24 / 15
5 0h:00m:00s -0.76ns 24 / 15
6 0h:00m:00s -0.76ns 24 / 15
------------------------------------------------------------
Net buffering Report for view:work.match_rec(verilog):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 46MB)
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1212742801> | The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 46MB)
Writing Analyst data base E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1212742801> | Writing default property annotation file E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.map.
Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/netattr.txt>
Version 8.8.0.4
Found clock match_rec|clk with period 2.13ns
<a name=timingReport3>##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 06 17:00:01 2008
#
Top view: match_rec
Requested Frequency: 469.2 MHz
Wire load mode: top
Paths requested: 0
Constraint File(s): E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.sdc
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1212742801> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1212742801> | Clock constraints cover only FF-to-FF paths associated with the clock..
<a name=performanceSummary4>Performance Summary
*******************
Worst slack in design: -0.376
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------
match_rec|clk 469.2 MHz 398.8 MHz 2.132 2.508 -0.376 inferred Autoconstr_clkgroup_0
========================================================================================================================
<a name=clockRelationships5>Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------------
match_rec|clk match_rec|clk | 2.132 -0.376 | No paths - | No paths - | No paths -
=====================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
<a name=interfaceInfo6>Interface Information
*********************
No IO constraint found
##### END OF TIMING REPORT #####]
---------------------------------------
<a name=resourceUsage7>Resource Usage Report for match_rec
Mapping to part: xc4vsx35ff668-10
Cell usage:
FDE 2 uses
FDR 13 uses
LUT1 2 uses
LUT2 3 uses
LUT3 10 uses
LUT4 8 uses
I/O ports: 5
I/O primitives: 4
IBUF 2 uses
OBUF 2 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 15 (0%)
Global Clock Buffers: 1 of 32 (3%)
Total load per clock:
match_rec|clk: 15
Mapping Summary:
Total LUTs: 23 (0%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 06 17:00:01 2008
###########################################################]
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