match_rec.plg

来自「使用VERILOG实现QPSK信号的匹配滤波」· PLG 代码 · 共 13 行

@P:  Worst Slack : -0.376
@P:  match_rec|clk - Estimated Frequency : 398.8 MHz
@P:  match_rec|clk - Requested Frequency : 469.2 MHz
@P:  match_rec|clk - Estimated Period : 2.508
@P:  match_rec|clk - Requested Period : 2.132
@P:  match_rec|clk - Slack : -0.376
@P: match_rec Part : xc4vsx35ff668-10
@P: match_rec I/O primitives : 4
@P: match_rec I/O Register bits : 0
@P: match_rec Register bits (Non I/O) : 15 (0%)
@P: match_rec Total Luts : 23 (0%)
@P:  CPU Time : 0h:00m:00s