📄 d__program_fpga_software_modelsim_xilinx_lib_unisims_ver__info
字号:
31o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t10_@x@a@u@i_4vGT11IQlcSOfC?MgAD4OS?]b>V;2VCM;4cDgcZ;OL6MHT:RVKB3dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 11374VCM;4cDgcZ;OL6MHT:RVKB3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11vGT11_CUSTOMIU022XU?5@_I<PF6>]g[FK2VKBLnZig=dSHakoGJAPoG[1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 14167VKBLnZig=dSHakoGJAPoG[1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11_@c@u@s@t@o@mvGT11_DUALISSCncPOHE[ogzNVlifU781Vkb`aF:5OE;1olkVRAh6jN3dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 14857Vkb`aF:5OE;1olkVRAh6jN3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11_@d@u@a@lvGT11_SWIFTINo3jI32THPQl3K<fT4?H^2V?m:hNABacDSl:Ccl4UjQJ1dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 8179V?m:hNABacDSl:Ccl4UjQJ1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11_@s@w@i@f@tvGT11_SWIFT_BITIdN3:`PY`1]Hf2e7gD3P^k0V]Szco6N4<215K[?gjdRJL1dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 10063V]Szco6N4<215K[?gjdRJL1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11_@s@w@i@f@t_@b@i@tvGT11CLKInDzE>P;fFD21_:0D_GTX91V?0gCj8UC@EOkE1e`2S_WN0dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 13964V?0gCj8UC@EOkE1e`2S_WN0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11@c@l@kvGT11CLK_MGTI=bL2icE;QL@M6Y^:`n68f0VSoA1Td@iWU0KA2R<LW7hT1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 14089VSoA1Td@iWU0KA2R<LW7hT1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t11@c@l@k_@m@g@tvGT_AURORA_1IWASQzaPna4LK<SS:`J85g0VXGY77P`hcZW>jGOF5dSOP1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 23690VXGY77P`hcZW>jGOF5dSOP1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@a@u@r@o@r@a_1vGT_AURORA_2I_ZA^bAYNe<@fPiCQ7IWlD0VP1:zk5E^PII1j33g4`81d1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 23961VP1:zk5E^PII1j33g4`81d1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@a@u@r@o@r@a_2vGT_AURORA_4I;A5m_j4LJ4Ti2DY6`3Q1I3VL@FafccB4c0>K=`6OSznB2dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 24232VL@FafccB4c0>K=`6OSznB2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@a@u@r@o@r@a_4vGT_CUSTOMI2^B8j`Y8lbeECk9Xh;mQ03VdYLSoRLnd?5[e;>R=P[X<1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 24495VdYLSoRLnd?5[e;>R=P[X<1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@c@u@s@t@o@mvGT_ETHERNET_1ISFYC<lgbVnF_WP;YDKYIP2VR:BOB4=>dC74A;0B@0Y060dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 24801VR:BOB4=>dC74A;0B@0Y060OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@e@t@h@e@r@n@e@t_1vGT_ETHERNET_2INP`kQKm2@oT3`MDdYaKGK3VOn:enPR`TVij6EUDckAgW2dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 25066VOn:enPR`TVij6EUDckAgW2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@e@t@h@e@r@n@e@t_2vGT_ETHERNET_4IPoDn1R?^IL3kQ`c86V3<I0V>cbcJ>k2PONa18g@S^^D^2dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 25331V>cbcJ>k2PONa18g@S^^D^2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@e@t@h@e@r@n@e@t_4vGT_FIBRE_CHAN_1IlCAD7bAWo16VB^ClUT1M53V[WYReYoD1^D8d_gL_LF;n1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 25588V[WYReYoD1^D8d_gL_LF;n1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@f@i@b@r@e_@c@h@a@n_1vGT_FIBRE_CHAN_2IUmWKl<PDZ>F@oEUOE7N8k0VT8=fQIWGe^G02aj1_@FH31dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 25853VT8=fQIWGe^G02aj1_@FH31OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@f@i@b@r@e_@c@h@a@n_2vGT_FIBRE_CHAN_4IfUlJH5:RJ4VLn_`e>^jD60VYR5fGe180Rlcnk[no3NST0dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 26118VYR5fGe180Rlcnk[no3NST0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@f@i@b@r@e_@c@h@a@n_4vGT_INFINIBAND_1IAbBgL=k@B5:YQH;U77QB00V_oULNTS0Z_>_bFhWPX@g`2dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 26373V_oULNTS0Z_>_bFhWPX@g`2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@i@n@f@i@n@i@b@a@n@d_1vGT_INFINIBAND_2I=?64L^cziX4>]k9FEBfAD1V^ZN7X0XEe0:^5K_EFF:hb3dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 26645V^ZN7X0XEe0:^5K_EFF:hb3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@i@n@f@i@n@i@b@a@n@d_2vGT_INFINIBAND_4IU882NRDO`;d<^]9;[:fc50V?GedYOfZS5V6d3aW^0eUV1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 26917V?GedYOfZS5V6d3aW^0eUV1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@i@n@f@i@n@i@b@a@n@d_4vGT_SWIFTI5hm?8]bbgZ:`]J[6aUf1W3V3:X=h@1Mki36j<bz<@fU03dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 32079V3:X=h@1Mki36j<bz<@fU03OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@s@w@i@f@tvGT_SWIFT_BITIXem70di4MnWf0<6Y1AD5^0VT]C@V0dQ[LG1:oni6O1dg1dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 32775VT]C@V0dQ[LG1:oni6O1dg1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@s@w@i@f@t_@b@i@tvGT_XAUI_1ILl@5i>?UPj0I[mdMae][W3VB>XcS79fO4EU<@CMbog_e2dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 27181VB>XcS79fO4EU<@CMbog_e2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@x@a@u@i_1vGT_XAUI_2ISI8ZM5^6WXEW13^efzTo:3VzVjK^Xa?30hzlIch>`XfF1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 27455VzVjK^Xa?30hzlIch>`XfF1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@x@a@u@i_2vGT_XAUI_4IIP@eGnbIHMABjVzi]l;MI3VmXKPcLi=T=1RWMPicgCCZ3dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 27729VmXKPcLi=T=1RWMPicgCCZ3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t_@x@a@u@i_4vGTP_DUALI`czIDm5J80MNTLhEc:dPz1VO@b5Oc2Uo[9<9Ci7@>F2]1dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 16223VO@b5Oc2Uo[9<9Ci7@>F2]1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t@p_@d@u@a@lvGTP_DUAL_SWIFTI[NJ8ORGB=K9a;]cmXK03`2Vk`Ja]4h2N4FzGS[9dAlC01dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 15937Vk`Ja]4h2N4FzGS[9dAlC01OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t@p_@d@u@a@l_@s@w@i@f@tvGTP_DUAL_SWIFT_BITI?6HSb;f64WLOAXSHHVo?m1V=g52^5YBS0NMm>k4@PFo_3dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 18025V=g52^5YBS0NMm>k4@PFo_3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t@p_@d@u@a@l_@s@w@i@f@t_@b@i@tvGTX_DUALIE?R?9X^j5j5bIz3c0[OSC3V:bU1XmONeWA2_<UXR?kbk2dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 19736V:bU1XmONeWA2_<UXR?kbk2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t@x_@d@u@a@lvGTX_DUAL_SWIFTI:zf9C_XhD`C^eKbS?T_@@2V;K>6P``ETibPD]AVFa8j;1dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 22691V;K>6P``ETibPD]AVFa8j;1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t@x_@d@u@a@l_@s@w@i@f@tvGTX_DUAL_SWIFT_BITI]dUGBM;9O[4O`MjPFP5S=0V`Xi]L@Z>E7^W39TgFNY_F2dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 25416V`Xi]L@Z>E7^W39TgFNY_F2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@g@t@x_@d@u@a@l_@s@w@i@f@t_@b@i@tvIBUFIKYkWiA><6>WW`SnO9Z2Bn3VY]OanAeP0BfPP1NNX?bEK0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 23947VY]OanAeP0BfPP1NNX?bEK0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@fvIBUF_AGPI5I7]h7MGhk2Vh4mCi]?;I0V9IYY^6G[m0>ZAGY>n77Ie1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27465V9IYY^6G[m0>ZAGY>n77Ie1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@a@g@pvIBUF_CTTIFkfKZB@bO`VUHO^^:MT];3V6bl@KkbKTdO^9d;SfVm[a3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27498V6bl@KkbKTdO^9d;SfVm[a3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@c@t@tvIBUF_DLY_ADJI2O5U8QFN?]GIeTaXZGKmZ0VU0e:hKgB>g`ECmZ_FMVB=1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27532VU0e:hKgB>g`ECmZ_FMVB=1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@d@l@y_@a@d@jvIBUF_GTLIYIGYYF<0H]K5[FSXQaiDH0V4l^DRQdzcL3^5KDN]DcJR0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27668V4l^DRQdzcL3^5KDN]DcJR0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@g@t@lvIBUF_GTL_DCIIngL5WJ:3RVTMdGD6;Zj5;2VB]9CLQANL7EJEPM^mB1_`3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27767VB]9CLQANL7EJEPM^mB1_`3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@g@t@l_@d@c@ivIBUF_GTLPI=meOmV=1BPT0QMGkdWL^G3VKSS]k[ME>TDA8F3778D5E2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27701VKSS]k[ME>TDA8F3778D5E2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@g@t@l@pvIBUF_GTLP_DCIIV:;8J1m6;eJeY1@OdnVZj1VAFKJ^3biiAg5TWIk=K0YK3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 27734VAFKJ^3biiAg5TWIk=K0YK3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@i@b@u@f_@g@t@l@p_@d@c@ivIBUF_HSTL_II=:O9A7MPNV[PQN6Cm4A9F0VJ[5UTGd4PMRmRO]C?A;5i2dC:\Documen⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -