📄 d__program_fpga_software_modelsim_xilinx_lib_unisims_ver__info
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VGfWYcazaKDO6c>M]cUcV30OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vervdcm_sp_maximum_period_checkIKAB2AfHhP<`h::3^Al<UP0VLLjC>57OXl43>L>B`eK1;2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 14073VLLjC>57OXl43>L>B`eK1;2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vervDNA_PORTIFmflJMK3Q9BAZBAUi`N1J1VJzzE?T4TQ<4=K<zNCk5?o2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 14229VJzzE?T4TQ<4=K<zNCk5?o2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@d@n@a_@p@o@r@tvDSP48I?MVoQXFi^b?hgUOQF<H1l1Vf>iCfGA?X7d_iWYbPldSM1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 14307Vf>iCfGA?X7d_iWYbPldSM1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@d@s@p48vDSP48AIHD@=imPNTUB_6@LVBch_33VhdfTKJFgNgRRDoCV;1[VO0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 15327VhdfTKJFgNgRRDoCV;1[VO0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@d@s@p48@avDSP48EI=<@kA?c6aNG`Fi3zXKcC13V>AZ49ABH]CBWd7SWS1M9H1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 16696V>AZ49ABH]CBWd7SWS1M9H1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@d@s@p48@evEMACIOF=KDQNhE^Q;YMWTMIT@k2V[CHXkmT8cKQmBM44l@L290dC:\Documents and Settings\userw1212132288FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SMART_source.vL0 331V[CHXkmT8cKQmBM44l@L290OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@e@m@a@cvEMAC_SWIFTID:QcOnkAQHPlN>nnAi<E=3VQb;3]]NYQgR<5A]eEfna_3dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 371VQb;3]]NYQgR<5A]eEfna_3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@e@m@a@c_@s@w@i@f@tvEMAC_SWIFT_BITIz=F0UULKjQCRHl1OeM`QM0V1`<TP=d3JQo>J27:Ujd@G1dC:\Documents and Settings\userw1212132283FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_SmartWrapper_source.vL0 1444V1`<TP=d3JQo>J27:Ujd@G1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@e@m@a@c_@s@w@i@f@t_@b@i@tvFDI8ge3a`hcUT5ITT9d1TBQO3V]=`@WnhCcWRISOCL<F;N:1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19575V]=`@WnhCcWRISOCL<F;N:1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@dvFD_1IQSWT2Lm8lIiQZ3lDYkgaY3V4d<:m=0GTgnY:bIB1iel42dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21516V4d<:m=0GTgnY:bIB1iel42OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d_1vFDCIJ75W]:?nD63TG2VKTTHZ>0Va8czLUR[6cbmXI]`=@O0R1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19634Va8czLUR[6cbmXI]`=@O0R1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@cvFDC_1IQT>a?0H0O1<6GQ=?Rfi1A1VA3_F6F>Bj[NGmYWNX];=X3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20082VA3_F6F>Bj[NGmYWNX];=X3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c_1vFDCEI?_M45?VEUP4^Ne@D0?a0W1V2mcGf8[Ki3;RPf:AfNY^M2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19694V2mcGf8[Ki3;RPf:AfNY^M2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c@evFDCE_1IDj7Ge]SO0k4JzbQ60`0mW1V2?OcN:>8fMBnBIdC6TiVY1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19758V2?OcN:>8fMBnBIdC6TiVY1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c@e_1vFDCPICeWdHe4:l`_aT8Jo32D[U1V;YWcn?ebj2VgAe<c=HRgN3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19821V;YWcn?ebj2VgAe<c=HRgN3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c@pvFDCP_1I6?`e^REC<XMCJ@eYdQ?bz0V`MYUDC`7BF6QQJP@Sf1OB2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20016V`MYUDC`7BF6QQJP@Sf1OB2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c@p_1vFDCPEI[iUXLf=<77GJSmNfznH`>3VB;XI^:?<H0iKzDKhAKg^F3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19886VB;XI^:?<H0iKzDKhAKg^F3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c@p@evFDCPE_1I1Ea3Y<mK8[>Yn;>Y4g1VZ2V0l8]N>kmhk>2aIIZ_5Bca0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 19951V0l8]N>kmhk>2aIIZ_5Bca0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@c@p@e_1vFDDRCPEIlRAU0PnaDhm<;94l1<WgH2Vhb5R1fV5785R[LN>1>fKf2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20144Vhb5R1fV5785R[LN>1>fKf2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@d@r@c@p@evFDDRRSEIYQeheBJFW<CTh]cgeKJea0V9ZkoEhPP:SQU9in8A2lKI3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20259V9ZkoEhPP:SQU9in8A2lKI3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@d@r@r@s@evFDEIT^Z^dLYNdb2]ihZUijng22VU=G0aWQg@>GC3IGb5?iLF3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20376VU=G0aWQg@>GC3IGb5?iLF3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@evFDE_1IE:O3@3GYYHGl@4hQ67CVz0VeLPFJ50k]>Nj9TH<L[CM>0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20434VeLPFJ50k]>Nj9TH<L[CM>0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@e_1vFDPImM6=GUPGkj=P1;HFO<5m90VmLL0H]iVj9SFij5;U`Jdi1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20495VmLL0H]iVj9SFij5;U`Jdi1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@pvFDP_1IGFXReML69PFGHS@6BI`YR3VLXRjjP<A8VL16IFJYUBcD3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20684VLXRjjP<A8VL16IFJYUBcD3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@p_1vFDPEIP>TkXdP4dF5W3RNeY=Izg1VgdL[f0^Rb2>MIBH1C6AfW3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20556VgdL[f0^Rb2>MIBH1C6AfW3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@p@evFDPE_1I]XLPdo1W>XH:B<ZU_QTd:0VYZ:lFIfhDmHh^5fa44`6l3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20620VYZ:lFIfhDmHh^5fa44`6l3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@p@e_1vFDRITcc6hL9iAX?2^12FM>jGH3Vn?f]mYdgNF_lLZY5N8fS10dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20746Vn?f]mYdgNF_lLZY5N8fS10OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@rvFDR_1IkLT]L77>OM`gGg6m;XZn22Vbf;8XUHWeE6PCj4dT1Q5F0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21201Vbf;8XUHWeE6PCj4dT1Q5F0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r_1vFDREI=[a[I@4KjC9F?iM]6kNzU1Vg4;ZUCh]RQOk:czQKbjAc3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20808Vg4;ZUCh]RQOk:czQKbjAc3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r@evFDRE_1I[<R2:kkIgB3SXgbZV41a^2VDa=Y869Nka[3Bz<B]?VY62dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20872VDa=Y869Nka[3Bz<B]?VY62OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r@e_1vFDRSI4KGbk7IgX57XH12>acZ^D2VbXjToF9XV7bPXQmnFoz5d2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 20935VbXjToF9XV7bPXQmnFoz5d2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r@svFDRS_1IKE>1YC?A:0lGWGCdNGFW^3VZFTT27WRkil9`NiQd]aO^2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21134VZFTT27WRkil9`NiQd]aO^2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r@s_1vFDRSEI6HG;f4T?cdmdWY1ff<okj2VcjSjkX360GXz;`2Ef_mJI0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21002VcjSjkX360GXz;`2Ef_mJI0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r@s@evFDRSE_1ITBEP6k1EfQB5>YcUie^kb1V^FEiKSegTHgJkZKWUX[423dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21068V^FEiKSegTHgJkZKWUX[423OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@r@s@e_1vFDSIM7QPV5C6QMR7WXfnG]09c0VDNh]QUMY0ClaG`aUzi17=3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21264VDNh]QUMY0ClaG`aUzi17=3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@svFDS_1IL5_0zc7J>[60GcoQI1L5F2VW3EoB9D0WSI]MUl>K@YYl2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21453VW3EoB9D0WSI]MUl>K@YYl2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@s_1vFDSEIH49;C0eb23Tm0^l17WlB]2VL68jz[?MDj2=N1G3o75783dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21327VL68jz[?MDj2=N1G3o75783OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@s@evFDSE_1IF`OPdmdz9@gRP0PclB>?c1VS><[;d@8K_[3V13B1ZoeX1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21390VS><[;d@8K_[3V13B1ZoeX1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@d@s@e_1vFIFO16IXeM5Q7f0B1XBK_5ZgGLWD2V4bTcKf]`PlL=N[[dk4n9c3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 21572V4bTcKf]`PlL=N[[dk4n9c3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@f@i@f@o16vFIFO18I6l`8cDB@eMM>nY;Y;LJ]h2V=`U2oJXbdI?>29:GSP=BZ2⌨️ 快捷键说明
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