📄 d__program_fpga_software_modelsim_xilinx_lib_unisims_ver__info
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m25513cModel Technology
dC:\Documents and Settings\user
vAFIFO36_INTERNALI3[[CgUG_V18zY2Y]o=FaO0V>ORenHWF[H[0YCiBdNCB>3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 29V>ORenHWF[H[0YCiBdNCB>3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@f@i@f@o36_@i@n@t@e@r@n@a@lvAND2IVPF<k1SkcXn6jN@Y]HE3=3V6c3CLD=ocPgUkX1kkzMQZ0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 1813V6c3CLD=ocPgUkX1kkzMQZ0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d2vAND2B1I0;bLOAJGRmSn]H9]8BQ3h1V1g;B]iTNDjzdSX48g:FYX2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 1846V1g;B]iTNDjzdSX48g:FYX2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d2@b1vAND2B2I[D=:;HEVz3F;3nnVHXYRE3V?Oi[IV3E>NggMGc>zn8bj3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 1883V?Oi[IV3E>NggMGc>zn8bj3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d2@b2vAND3Ihd0@fO@g:?fPCmWbT14D91V`@^o1^z^<XEb<0E7lzk<V2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 1921V`@^o1^z^<XEb<0E7lzk<V2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d3vAND3B1IGLzS3T[[D`1BVz^K<hFhK3V]hVc5e_kBgD47?PXcIY2_0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 1955V]hVc5e_kBgD47?PXcIY2_0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d3@b1vAND3B2I>i:VPT?NZhN;E[E@?M2U02VPHHe`;_>OYHiOVo5C:c4U0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 1992VPHHe`;_>OYHiOVo5C:c4U0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d3@b2vAND3B3IOkT6__O_0g9bLRUF8Y4I70V2f5WB=LEgc]Z2gaQZHgF82dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2031V2f5WB=LEgc]Z2gaQZHgF82OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d3@b3vAND4IJeAlRM>K68lzRanRfX[E01VfAfX6aM3o01DOKT8NzF0M0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2071VfAfX6aM3o01DOKT8NzF0M0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d4vAND4B1I=9DN0^WfLU^k4gZco4Cam2V<Yd7LdW6X<2DRcS3;<3Pj3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2105V<Yd7LdW6X<2DRcS3;<3Pj3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d4@b1vAND4B2IMH?OCb^K`>o>fJg=1hdMK0VO5a^NlHT0<9OcRUX3>1NA0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2142VO5a^NlHT0<9OcRUX3>1NA0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d4@b2vAND4B3IkY6UCgdUfdBInA>KLhWo_2V=HhT9nb=2^84XYH]P>]031dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2181V=HhT9nb=2^84XYH]P>]031OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d4@b3vAND4B4I_>GlRCEknmZeaDH04VU6c0VV90AkA^I_Jhf9h3ZdGEKT2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2222VV90AkA^I_Jhf9h3ZdGEKT2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d4@b4vAND5I@a6XkKCPZiaA3mLZ4cfa62VAlLjRhC2^d0>BUbX>mSdo0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2264VAlLjRhC2^d0>BUbX>mSdo0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d5vAND5B1IF8XB4A<@FQ@XSl5_ATP?03VAEmCUL;@DXi_h4T4W06OE2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2298VAEmCUL;@DXi_h4T4W06OE2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d5@b1vAND5B2I7U>bei>XHPmnCMhadWK@81V=T88bK9b`DUB9NCZzJecG2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2335V=T88bK9b`DUB9NCZzJecG2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d5@b2vAND5B3IKg6fXbR_=eaZ92Xf?KeOT3Vm0Ko_XKXk2b9CJRLQ[jHF3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2374Vm0Ko_XKXk2b9CJRLQ[jHF3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d5@b3vAND5B4IZbng@7UPc00RYZGTI_NKb2VNC?@fI;X?5@96PY:0Sd7C1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2415VNC?@fI;X?5@96PY:0Sd7C1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d5@b4vAND5B5IYXBg5@lMSeV04kR9j<;GF3VADGZGO3am59C9W<g6kE1M2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2458VADGZGO3am59C9W<g6kE1M2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@n@d5@b5vARAMB36_INTERNALIW2?iX6T>jg3SSaC4_Z1Y>0V9`7k8eC]L0Nc2244D6]Am3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 2523V9`7k8eC]L0Nc2244D6]Am3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@a@r@a@m@b36_@i@n@t@e@r@n@a@lvBSCAN_FPGACOREIjh]8j7=;K`QcHWgV5hUeF2Vf[<<mh@1kK;P`RVY9L7Cc1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 5766Vf[<<mh@1kK;P`RVY9L7Cc1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@f@p@g@a@c@o@r@evBSCAN_SPARTAN2IVeeh^LMU9?2THC8@Th9fG1VgLAETY6BMJ97X2]0m`gY10dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 5806VgLAETY6BMJ97X2]0m`gY10OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@s@p@a@r@t@a@n2vBSCAN_SPARTAN3I_m1ShJ[U1Q3Fz<Jh8cGJR3Vbl9`G^JIU7lj;=MCi25ji2dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 5846Vbl9`G^JIU7lj;=MCi25ji2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@s@p@a@r@t@a@n3vBSCAN_SPARTAN3AI_KTfJhl]]nWL]0j5G?Bmm2VmjA@eLW>C`98OnKohM5n71dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 5885VmjA@eLW>C`98OnKohM5n71OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@s@p@a@r@t@a@n3@avBSCAN_VIRTEXI7Oh4VTd7GkBfAifHd8S;l0V0IbhZVWH0KJQ_>P7>GDO>1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 5958V0IbhZVWH0KJQ_>P7>GDO>1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@v@i@r@t@e@xvBSCAN_VIRTEX2IfRd>?DCeI;zYi[9<^Q`SY1VH92m2I:8LCkmo4WL0`P<g0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 5998VH92m2I:8LCkmo4WL0`P<g0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@v@i@r@t@e@x2vBSCAN_VIRTEX4I=nKOa]o7iH[5z<R8TN4i;0VYKfJM<I7BbZ?0RQDhZgjK3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6041VYKfJM<I7BbZ?0RQDhZgjK3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@v@i@r@t@e@x4vBSCAN_VIRTEX5IQz[_H0jeQYUfAl6_0zYm=3VcDdW9ai24=2VnB8Mdg1OH3dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6127VcDdW9ai24=2VnB8Mdg1OH3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@s@c@a@n_@v@i@r@t@e@x5vBUFIKmSbYQi`2jd^J^f_aTOVi1V=P9@7mL`>LfK@lcTomGRJ1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6216V=P9@7mL`>LfK@lcTomGRJ1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@fvBUFCFIoLY8YdCgE0NYS9=bT=P]R0V8NmMf;;gJCeVaEfYXGZOK0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6249V8NmMf;;gJCeVaEfYXGZOK0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@c@fvBUFEIj4^KXdFWa<@RMH][L9C>33V0LL1X8jX2AeH];>dPkJR30dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6282V0LL1X8jX2AeH];>dPkJR30OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@evBUFGI89SZgO5^F8V42VfiHUmBZ3VMj:8Ah3C?ZnVZaXFhjOhJ0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6315VMj:8Ah3C?ZnVZaXFhjOhJ0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@gvBUFGCEI?H?4FjZ5TRo[C;oma0@Sf2VDKBIdeheAQmZb35=eZGjC0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6347VDKBIdeheAQmZb35=eZGjC0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@c@evBUFGCE_1I<Of=>Cm?8_g>T1>;H<2B]1VeGB8[DZ<G4Q0A]z3CRa^c1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6385VeGB8[DZ<G4Q0A]z3CRa^c1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@c@e_1vBUFGCTRLIY5iS:P;IQYO_U?GK_dheT1VCfon2jhZWD?MNc3HDS8>n0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6425VCfon2jhZWD?MNc3HDS8>n0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@c@t@r@lvBUFGDLLI8ZzHZCV1Kh<;Y^>f4WIJ20V7Ejj[c39zH<XKCk9Q:jDm1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6590V7Ejj[c39zH<XKCk9Q:jDm1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@d@l@lvBUFGMUXIGYLe?zoF0O4a8`8FE?0n82VbAXg1zd1^e6d[SeOQn;7Z0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6631VbAXg1zd1^e6d[SeOQn;7Z0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@m@u@xvBUFGMUX_1I8^HWPTQIzMO[VZ:WLfCd]2VjYP[`<LQ6a?5Q^J^F@7]N0dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6696VjYP[`<LQ6a?5Q^J^F@7]N0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@m@u@x_1vBUFGMUX_CTRLIK]UT1`BH5E2?QhXO:0MF=2VLAQRS^aC>6>0067fWBn5Z1dC:\Documents and Settings\userw1212132127FD:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_ver\unisims_ver_source.vL0 6760VLAQRS^aC>6>0067fWBn5Z1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\unisims_vern@b@u@f@g@m@u@x_@c@t@r@lvBUFGMUX_VIRTEX4IB8;;bSfW:<8nTmF[_DdIh2V[I@;f3Ac5zH5ciBS;JMO=1
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