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来自「用FPGA verilog hdl实现千兆以太网MAC。」· 代码 · 共 17 行
TXT
17 行
/1000Mbps_duplex.vec/1.1/Sat Jul 26 07:29:32 2008///100Mbps_duplex.vec/1.1/Sat Jul 26 07:29:32 2008///10Mbps_duplex.vec/1.1/Sat Jul 26 07:29:32 2008///46-100.ini/1.1/Sat Jul 26 07:29:32 2008///46-46.ini/1.1/Sat Jul 26 07:29:32 2008///46-50.ini/1.1/Sat Jul 26 07:29:32 2008///46-80.ini/1.1/Sat Jul 26 07:29:32 2008///47-47.ini/1.1/Sat Jul 26 07:29:32 2008///48-48.ini/1.1/Sat Jul 26 07:29:32 2008///CPU.vec/1.1/Sat Jul 26 07:29:32 2008///batch.dat/1.1/Sat Jul 26 07:29:32 2008///config.ini/1.1/Sat Jul 26 07:29:32 2008///flow_ctrl.vec/1.1/Sat Jul 26 07:29:32 2008///source_mac_replace.vec/1.1/Sat Jul 26 07:29:32 2008///target_mac_check.vec/1.1/Sat Jul 26 07:29:32 2008//D
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