entries

用FPGA verilog hdl实现千兆以太网MAC。

/Phy_sim.v/1.3/Fri Nov 17 17:53:07 2006//
/User_int_sim.v/1.3/Fri Nov 17 17:53:07 2006//
/altera_mf.v/1.1/Thu Jan 19 14:07:50 2006//
/host_sim.v/1.1/Thu Jan 19 14:07:51 2006//
/reg_int_sim.v/1.1/Tue Dec 13 12:54:38 2005//
/tb_top.v/1.3/Thu Jan 19 14:07:51 2006//
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