📄 spi_controller_vhd.mht
字号:
From: <óé Windows Internet Explorer 7 ±￡′?>
Subject:
Date: Tue, 29 Jul 2008 18:43:41 +0800
MIME-Version: 1.0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Content-Location: http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/2002_w/interfacing/SPI/spi_controller.vhd
X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3138
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.5730.13" name=3DGENERATOR></HEAD>
<BODY><PRE>--------------------------------------------------------------=
--------
-- SPI_CONTROLLER
----------------------------------------------------------------------
-- This entity passes device driver data to and from the SPI_PHY. It
-- also initializes the clock to synchronize transmission on the bus.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SPI_Controller is
generic
(
data_width : positive :=3D 8
);
port
(
clock : in std_logic;
-- Device Driver Interface Signals
ready : in std_logic;
load, done : out std_logic;
driver_tx_data : in std_logic_vector(data_width-1 downto 0);
driver_rx_data : out std_logic_vector(data_width-1 downto 0);
-- SPI Bus Control Signals
SCLK : out std_logic;
bus_tx_data : out std_logic_vector(data_width-1 downto 0);
bus_rx_data : in std_logic_vector(data_width-1 downto 0)
-- SS : out std_logic_vector(num_devices-1 downto 0)
);
end entity SPI_Controller;
architecture mixed of SPI_Controller is
TYPE STATE_TYPE IS (wait_for_ready, set_SCLK_high,=20
set_SCLK_low, finished);
SIGNAL state, next_cycle: STATE_TYPE;
begin
bus_tx_data <=3D driver_tx_data;
driver_rx_data <=3D bus_rx_data;
Process_Transmission : process(clock) is
variable count : integer;
begin
IF ready =3D '0' THEN
load <=3D '1';
SCLK <=3D '0';
done <=3D '0'; =09
state <=3D wait_for_ready;
ELSIF rising_edge(clock) THEN
CASE state IS
-- Load Shift Registers and Prepare for Transmission
WHEN wait_for_ready =3D>
count :=3D 0;
state <=3D set_SCLK_high;
-- Initialize Clock (one extra clock added for loading data)
WHEN set_SCLK_high =3D>
SCLK <=3D '1';
-- Check if all data bits have been sent
IF count =3D data_width THEN
next_cycle <=3D finished;
-- If data bits remain send the next bit
ELSE
count :=3D count + 1;
next_cycle <=3D set_SCLK_high;
END IF;
state <=3D set_SCLK_low;
-- Inform Controller Transmission is complete
WHEN finished =3D>
done <=3D '1';
-- Pull SCLK Low to Complete Clock Cycle
WHEN set_SCLK_low =3D>
SCLK <=3D '0';
load <=3D '0';
state <=3D next_cycle;
END CASE;
END IF;
=09
end process;
end architecture mixed;
</PRE></BODY></HTML>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -