spi_phy_vhd.mht

来自「一篇比较好的spi接口的vhdl实现的参考」· MHT 代码 · 共 88 行

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<BODY><PRE>--------------------------------------------------------------=
--------
-- SPI_PHY
----------------------------------------------------------------------
-- This entity serializes data sent to the bus and parallelizes data
-- received from the bus.  It "talks" to other devices using standard
-- SPI protocol, however, bus arbitration must be handled elsewhere=20
-- (eg. SPI_Controller or other custom entity).
----------------------------------------------------------------------
-- KNOWN ISSUES:
--  * Currently only works for polarity=3D0, phase=3D1
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;

entity SPI_PHY is
generic
(
	data_width : positive :=3D 8;
	rising_edge_triggered : positive :=3D 1
);
port
(
	-- Control Signals
	clock, load : in std_logic;

	-- Data Register (put TX data in here before transmission,
	-- read RX data from here after transmission)
	dataTX : in std_logic_vector(data_width-1 downto 0);
	dataRX : out std_logic_vector(data_width-1 downto 0);

	-- SPI Data Interface
	MISO : in std_logic;
	MOSI, SCLK : out std_logic
);
end entity SPI_PHY;

architecture behaviour of SPI_PHY is
begin
=09
	sync_clock : process(clock) is
	begin
		if rising_edge_triggered =3D 1 then
			SCLK &lt;=3D clock AND NOT load;
		else
			SCLK &lt;=3D NOT clock AND NOT load;
		end if;
	end process sync_clock;

	shift_register : lpm_shiftreg
		generic map=20
		(
			LPM_WIDTH =3D&gt; data_width
		)
		port map
		(
			-- MISO - Receives and buffers data bit from slave device
			-- MOSI - Transmits buffered data bit to slave device
			-- LOAD - Load DATA into transmit buffer
			shiftin =3D&gt; MISO,
			load =3D&gt; load,
			data =3D&gt; dataTX,
			clock =3D&gt; clock,
			shiftout =3D&gt; MOSI,
			q =3D&gt; dataRX
		);

end architecture behaviour;
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