seg7.tan.rpt

来自「vhdl的很多例子」· RPT 代码 · 共 233 行 · 第 1/5 页

; Clock Setup: 'clk'           ; N/A   ; None          ; 179.60 MHz ( period = 5.568 ns ) ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[2] ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[21] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                         ;                                                                                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                     ; To                                                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 179.60 MHz ( period = 5.568 ns )                    ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[2]  ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[17] ; clk        ; clk      ; None                        ; None                      ; 4.859 ns                ;
; N/A                                     ; 179.60 MHz ( period = 5.568 ns )                    ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[2]  ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[18] ; clk        ; clk      ; None                        ; None                      ; 4.859 ns                ;
; N/A                                     ; 179.60 MHz ( period = 5.568 ns )                    ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[2]  ; lpm_counter0:inst12|lpm_counter:lpm_counter_component|cntr_had:auto_generated|safe_q[19] ; clk        ; clk      ; None                        ; None                      ; 4.859 ns                ;