int_div.vhd

来自「vhdl的很多例子」· VHDL 代码 · 共 31 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity int_div is
 PORT( clk  :  IN  STD_LOGIC;
       clk_out : OUT STD_LOGIC
 );
END int_div;

architecture behav of int_div is
constant CLK_FREQ  :   integer :=50000000;
constant DCLK_FREQ :   integer :=10;--产生5HZ的频率

SIGNAL DCLK_DIV :   integer range 0 to 50000000;
SIGNAL clk_tem  : STD_LOGIC;

begin
process (clk)
  begin
    if rising_edge(clk) then
      if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ)) then
          DCLK_DIV <= DCLK_DIV+1;
       else
          DCLK_DIV <= 0;
          clk_tem <= not clk_tem;
      end if;
   end if;
end process ;
clk_out<=clk_tem;

end behav;