serial.fit.rpt

vhdl的很多例子

; Number of Signals Sourced  (Average = 7.19) ; Number of LABs  (Total = 16) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 2                            ;
; 2                                           ; 1                            ;
; 3                                           ; 0                            ;
; 4                                           ; 2                            ;
; 5                                           ; 2                            ;
; 6                                           ; 0                            ;
; 7                                           ; 0                            ;
; 8                                           ; 0                            ;
; 9                                           ; 0                            ;
; 10                                          ; 7                            ;
; 11                                          ; 1                            ;
; 12                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 5.19) ; Number of LABs  (Total = 16) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 2                            ;
; 2                                               ; 1                            ;
; 3                                               ; 2                            ;
; 4                                               ; 3                            ;
; 5                                               ; 2                            ;
; 6                                               ; 1                            ;
; 7                                               ; 1                            ;
; 8                                               ; 1                            ;
; 9                                               ; 1                            ;
; 10                                              ; 1                            ;
; 11                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 8.13) ; Number of LABs  (Total = 16) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 1                            ;
; 3                                           ; 1                            ;
; 4                                           ; 2                            ;
; 5                                           ; 0                            ;
; 6                                           ; 2                            ;
; 7                                           ; 1                            ;
; 8                                           ; 3                            ;
; 9                                           ; 2                            ;
; 10                                          ; 0                            ;
; 11                                          ; 0                            ;
; 12                                          ; 2                            ;
; 13                                          ; 0                            ;
; 14                                          ; 1                            ;
; 15                                          ; 0                            ;
; 16                                          ; 0                            ;
; 17                                          ; 0                            ;
; 18                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Oct 24 21:58:44 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off serial -c serial
Info: Selected device EPM1270T144C5 for design "serial"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144C5ES is compatible
Info: No exact pin location assignment(s) for 6 pins of 12 total pins
    Info: Pin led[7] not assigned to an exact location on the device
    Info: Pin led[6] not assigned to an exact location on the device
    Info: Pin led[5] not assigned to an exact location on the device
    Info: Pin led[4] not assigned to an exact location on the device
    Info: Pin led[3] not assigned to an exact location on the device
    Info: Pin led[2] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "serial_test:inst|clkbaud8x" to use Global clock
    Info: Destination "serial_test:inst|clkbaud8x" may be non-global or may not use global clock
Info: Automatically promoted signal "reset" to use Global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 0 input, 6 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 3 total pin(s) used --  23 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 3 total pin(s) used --  27 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:05
Info: Estimated most critical path is register to pin delay of 3.984 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y8; Fanout = 3; REG Node = 'serial_test:inst|txd_reg'
    Info: 2: + IC(1.662 ns) + CELL(2.322 ns) = 3.984 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'txd_usb'
    Info: Total cell delay = 2.322 ns ( 58.28 % )
    Info: Total interconnect delay = 1.662 ns ( 41.72 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Oct 24 21:58:55 2006
    Info: Elapsed time: 00:00:13