i2c.map.eqn

vhdl的很多例子

B1_clk_div[0]_lut_out = B1L12 & (!B1L126 # !B1_clk_div[5] # !B1L116);
B1_clk_div[0] = DFFEAS(B1_clk_div[0]_lut_out, clk, reset, , , , , , );


--B1_clk_div[3] is i2c_test:inst|clk_div[3]
--operation mode is normal

B1_clk_div[3]_lut_out = B1L14 & (!B1L126 # !B1_clk_div[5] # !B1L116);
B1_clk_div[3] = DFFEAS(B1_clk_div[3]_lut_out, clk, reset, , , , , , );


--B1L274 is i2c_test:inst|phase2~36
--operation mode is normal

B1L274 = B1_clk_div[5] & B1_clk_div[0] & (!B1_clk_div[3]);


--G1_cout is delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout
--operation mode is normal

G1_cout_carry_eqn = G1L20;
G1_cout = !G1_cout_carry_eqn;


--G2_cout is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|cout
--operation mode is normal

G2_cout_carry_eqn = G2L20;
G2_cout = !G2_cout_carry_eqn;


--B1L143 is i2c_test:inst|main_state[1]~1948
--operation mode is normal

B1L143 = G1_cout & G2_cout & write & rd;


--B1_cnt_delay[17] is i2c_test:inst|cnt_delay[17]
--operation mode is normal

B1_cnt_delay[17]_lut_out = B1L16;
B1_cnt_delay[17] = DFFEAS(B1_cnt_delay[17]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[16] is i2c_test:inst|cnt_delay[16]
--operation mode is normal

B1_cnt_delay[16]_lut_out = B1L18;
B1_cnt_delay[16] = DFFEAS(B1_cnt_delay[16]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[15] is i2c_test:inst|cnt_delay[15]
--operation mode is normal

B1_cnt_delay[15]_lut_out = B1L20;
B1_cnt_delay[15] = DFFEAS(B1_cnt_delay[15]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[14] is i2c_test:inst|cnt_delay[14]
--operation mode is normal

B1_cnt_delay[14]_lut_out = B1L22;
B1_cnt_delay[14] = DFFEAS(B1_cnt_delay[14]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1L118 is i2c_test:inst|Equal~528
--operation mode is normal

B1L118 = !B1_cnt_delay[17] & !B1_cnt_delay[16] & !B1_cnt_delay[15] & !B1_cnt_delay[14];


--B1_cnt_delay[11] is i2c_test:inst|cnt_delay[11]
--operation mode is normal

B1_cnt_delay[11]_lut_out = B1L24;
B1_cnt_delay[11] = DFFEAS(B1_cnt_delay[11]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[9] is i2c_test:inst|cnt_delay[9]
--operation mode is normal

B1_cnt_delay[9]_lut_out = B1L26;
B1_cnt_delay[9] = DFFEAS(B1_cnt_delay[9]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[7] is i2c_test:inst|cnt_delay[7]
--operation mode is normal

B1_cnt_delay[7]_lut_out = B1L28;
B1_cnt_delay[7] = DFFEAS(B1_cnt_delay[7]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[6] is i2c_test:inst|cnt_delay[6]
--operation mode is normal

B1_cnt_delay[6]_lut_out = B1L30;
B1_cnt_delay[6] = DFFEAS(B1_cnt_delay[6]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1L119 is i2c_test:inst|Equal~529
--operation mode is normal

B1L119 = !B1_cnt_delay[11] & !B1_cnt_delay[9] & !B1_cnt_delay[7] & !B1_cnt_delay[6];


--B1_cnt_delay[5] is i2c_test:inst|cnt_delay[5]
--operation mode is normal

B1_cnt_delay[5]_lut_out = B1L32;
B1_cnt_delay[5] = DFFEAS(B1_cnt_delay[5]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[4] is i2c_test:inst|cnt_delay[4]
--operation mode is normal

B1_cnt_delay[4]_lut_out = B1L34;
B1_cnt_delay[4] = DFFEAS(B1_cnt_delay[4]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[3] is i2c_test:inst|cnt_delay[3]
--operation mode is normal

B1_cnt_delay[3]_lut_out = B1L36;
B1_cnt_delay[3] = DFFEAS(B1_cnt_delay[3]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[2] is i2c_test:inst|cnt_delay[2]
--operation mode is normal

B1_cnt_delay[2]_lut_out = B1L38;
B1_cnt_delay[2] = DFFEAS(B1_cnt_delay[2]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1L120 is i2c_test:inst|Equal~530
--operation mode is normal

B1L120 = !B1_cnt_delay[5] & !B1_cnt_delay[4] & !B1_cnt_delay[3] & !B1_cnt_delay[2];


--B1_cnt_delay[1] is i2c_test:inst|cnt_delay[1]
--operation mode is normal

B1_cnt_delay[1]_lut_out = B1L40;
B1_cnt_delay[1] = DFFEAS(B1_cnt_delay[1]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[0] is i2c_test:inst|cnt_delay[0]
--operation mode is normal

B1_cnt_delay[0]_lut_out = B1L42 & (!B1L124 # !B1L122);
B1_cnt_delay[0] = DFFEAS(B1_cnt_delay[0]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1L121 is i2c_test:inst|Equal~531
--operation mode is normal

B1L121 = !B1_cnt_delay[1] & !B1_cnt_delay[0];


--B1L122 is i2c_test:inst|Equal~532
--operation mode is normal

B1L122 = B1L118 & B1L119 & B1L120 & B1L121;


--B1_cnt_delay[19] is i2c_test:inst|cnt_delay[19]
--operation mode is normal

B1_cnt_delay[19]_lut_out = B1L44 & (!B1L124 # !B1L122);
B1_cnt_delay[19] = DFFEAS(B1_cnt_delay[19]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[18] is i2c_test:inst|cnt_delay[18]
--operation mode is normal

B1_cnt_delay[18]_lut_out = B1L45 & (!B1L124 # !B1L122);
B1_cnt_delay[18] = DFFEAS(B1_cnt_delay[18]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[13] is i2c_test:inst|cnt_delay[13]
--operation mode is normal

B1_cnt_delay[13]_lut_out = B1L47 & (!B1L124 # !B1L122);
B1_cnt_delay[13] = DFFEAS(B1_cnt_delay[13]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[12] is i2c_test:inst|cnt_delay[12]
--operation mode is normal

B1_cnt_delay[12]_lut_out = B1L49 & (!B1L124 # !B1L122);
B1_cnt_delay[12] = DFFEAS(B1_cnt_delay[12]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1L123 is i2c_test:inst|Equal~533
--operation mode is normal

B1L123 = B1_cnt_delay[19] & B1_cnt_delay[18] & B1_cnt_delay[13] & B1_cnt_delay[12];


--B1_cnt_delay[10] is i2c_test:inst|cnt_delay[10]
--operation mode is normal

B1_cnt_delay[10]_lut_out = B1L51 & (!B1L124 # !B1L122);
B1_cnt_delay[10] = DFFEAS(B1_cnt_delay[10]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1_cnt_delay[8] is i2c_test:inst|cnt_delay[8]
--operation mode is normal

B1_cnt_delay[8]_lut_out = B1L53 & (!B1L124 # !B1L122);
B1_cnt_delay[8] = DFFEAS(B1_cnt_delay[8]_lut_out, clk, reset, , B1_start_delaycnt, , , , );


--B1L124 is i2c_test:inst|Equal~534
--operation mode is normal

B1L124 = B1L123 & B1_cnt_delay[10] & B1_cnt_delay[8];


--B1L144 is i2c_test:inst|main_state[1]~1949
--operation mode is normal

B1L144 = B1L143 # !B1L124 # !B1L122;


--B1_inner_state[1] is i2c_test:inst|inner_state[1]
--operation mode is normal

B1_inner_state[1]_lut_out = B1_main_state[0] & B1L173 # !B1_main_state[0] & (B1_main_state[1] & B1L176);
B1_inner_state[1] = DFFEAS(B1_inner_state[1]_lut_out, clk, reset, , , , , , );


--B1_inner_state[2] is i2c_test:inst|inner_state[2]
--operation mode is normal

B1_inner_state[2]_lut_out = B1_main_state[0] & B1L179 # !B1_main_state[0] & (B1_main_state[1] & B1L184);
B1_inner_state[2] = DFFEAS(B1_inner_state[2]_lut_out, clk, reset, , , , , , );


--B1L165 is i2c_test:inst|Mux~22852
--operation mode is normal

B1L165 = !B1_inner_state[1] & !B1_inner_state[2];


--B1_i2c_state[0] is i2c_test:inst|i2c_state[0]
--operation mode is normal

B1_i2c_state[0]_lut_out = B1_main_state[0] & (B1_main_state[1] & (B1_i2c_state[0]) # !B1_main_state[1] & B1L270) # !B1_main_state[0] & B1L270 & (B1_main_state[1]);
B1_i2c_state[0] = DFFEAS(B1_i2c_state[0]_lut_out, clk, reset, , , , , , );


--B1_i2c_state[1] is i2c_test:inst|i2c_state[1]
--operation mode is normal

B1_i2c_state[1]_lut_out = B1_i2c_state[1] & (B1L186 & B1L187 # !B1L169) # !B1_i2c_state[1] & B1L186 & B1L187;
B1_i2c_state[1] = DFFEAS(B1_i2c_state[1]_lut_out, clk, reset, , , , , , );


--B1_inner_state[0] is i2c_test:inst|inner_state[0]
--operation mode is normal

B1_inner_state[0]_lut_out = B1_main_state[1] & (B1L201 # B1_main_state[0] & B1L197) # !B1_main_state[1] & B1_main_state[0] & B1L197;
B1_inner_state[0] = DFFEAS(B1_inner_state[0]_lut_out, clk, reset, , , , , , );


--B1_phase3 is i2c_test:inst|phase3
--operation mode is normal

B1_phase3_lut_out = B1_phase3 # B1L128;
B1_phase3 = DFFEAS(B1_phase3_lut_out, clk, reset, , , , , B1_phase3, );


--B1L145 is i2c_test:inst|main_state[1]~1950
--operation mode is normal

B1L145 = B1_inner_state[2] & B1_inner_state[0] # !B1_inner_state[2] & B1_inner_state[1] & (B1_inner_state[0] # B1_phase3);


--B1_inner_state[3] is i2c_test:inst|inner_state[3]
--operation mode is normal

B1_inner_state[3]_lut_out = B1L267 & (B1L266 & (B1_inner_state[3]) # !B1L266 & B1L269) # !B1L267 & B1L269 & (B1L266);
B1_inner_state[3] = DFFEAS(B1_inner_state[3]_lut_out, clk, reset, , , , , , );


--B1_phase1 is i2c_test:inst|phase1
--operation mode is normal

B1_phase1_lut_out = B1_phase1 # B1L129;
B1_phase1 = DFFEAS(B1_phase1_lut_out, clk, reset, , , , , B1_phase1, );


--B1_sda_buf is i2c_test:inst|sda_buf
--operation mode is normal

B1_sda_buf_lut_out = B1_main_state[0] & !B1L227 # !B1_main_state[0] & (!B1L248 & B1_main_state[1]);
B1_sda_buf = DFFEAS(B1_sda_buf_lut_out, clk, reset, , , , , , );


--B1L146 is i2c_test:inst|main_state[1]~1951
--operation mode is normal

B1L146 = B1_inner_state[3] & (B1_phase1 & !B1_sda_buf # !B1_inner_state[0]);


--B1L147 is i2c_test:inst|main_state[1]~1952
--operation mode is normal

B1L147 = B1L146 & (B1_inner_state[0] $ (B1_i2c_state[1] & B1L145));


--B1L148 is i2c_test:inst|main_state[1]~1953
--operation mode is normal

B1L148 = B1_i2c_state[1] & (!B1_i2c_state[0] & !B1L147) # !B1_i2c_state[1] & (!B1L147 # !B1L165);


--B1_i2c_state[2] is i2c_test:inst|i2c_state[2]
--operation mode is normal

B1_i2c_state[2]_lut_out = B1_i2c_state[2] & (!B1L250) # !B1_i2c_state[2] & B1L249;
B1_i2c_state[2] = DFFEAS(B1_i2c_state[2]_lut_out, clk, reset, , !B1_main_state[0], , , !B1_main_state[1], );


--B1L149 is i2c_test:inst|main_state[1]~1954
--operation mode is normal

B1L149 = B1_main_state[0] & (B1L148 & !B1_i2c_state[2]) # !B1_main_state[0] & B1L144;


--B1L166 is i2c_test:inst|Mux~22853
--operation mode is normal

B1L166 = B1_i2c_state[2] & B1_i2c_state[0];


--B1L150 is i2c_test:inst|main_state[1]~1955
--operation mode is normal

B1L150 = B1_inner_state[3] & (!B1_inner_state[2]);


--B1L167 is i2c_test:inst|Mux~22854
--operation mode is normal

B1L167 = B1_phase3 & (!B1_inner_state[0]);


--B1L151 is i2c_test:inst|main_state[1]~1956
--operation mode is normal

B1L151 = !B1L167 # !B1L150 # !B1_i2c_state[0] # !B1_inner_state[1];


--B1L168 is i2c_test:inst|Mux~22855
--operation mode is normal

B1L168 = B1_inner_state[0] & (!B1_inner_state[1] & !B1_inner_state[2]);


--B1L152 is i2c_test:inst|main_state[1]~1957
--operation mode is normal

B1L152 = B1_sda_buf # !B1L168 # !B1_inner_state[3] # !B1_phase1;


--B1L153 is i2c_test:inst|main_state[1]~1958
--operation mode is normal

B1L153 = B1L166 # B1_i2c_state[1] & B1L151 # !B1_i2c_state[1] & (B1L152);


--B1L154 is i2c_test:inst|main_state[1]~1959
--operation mode is normal

B1L154 = B1_main_state[1] & (B1L153 & !B1_main_state[0]) # !B1_main_state[1] & B1L149;


--C1_inst4 is delay_reset_block:inst2|inst4
--operation mode is normal

C1_inst4 = !write # !G1_cout;


--B1L125 is i2c_test:inst|Equal~535
--operation mode is normal

B1L125 = B1_clk_div[6] & !B1_clk_div[2] & !B1_clk_div[7] & !B1_clk_div[4];


--B1L294 is i2c_test:inst|readData_reg[6]~415
--operation mode is normal

B1L294 = B1_i2c_state[1] & B1_i2c_state[0] & !B1_i2c_state[2];


--B1L295 is i2c_test:inst|readData_reg[6]~416
--operation mode is normal

B1L295 = !B1_inner_state[0] & !B1_inner_state[1];


--B1L296 is i2c_test:inst|readData_reg[6]~417
--operation mode is normal

B1L296 = B1_main_state[0] # B1_inner_state[3] $ (!B1_inner_state[2] & B1L295);


--B1L297 is i2c_test:inst|readData_reg[6]~418
--operation mode is normal

B1L297 = B1_main_state[1] & B1_phase1 & B1L294 & !B1L296;


--D1_counter[0] is i2c_t:inst4|counter[0]
--operation mode is normal

D1_counter[0]_lut_out = !D1_counter[0];
D1_counter[0] = DFFEAS(D1_counter[0]_lut_out, C1_inst4, reset, , , , , , );


--B1L169 is i2c_test:inst|Mux~22856
--operation mode is normal

B1L169 = !B1_main_state[1] & !B1_main_state[0];


--D1_counter[1] is i2c_t:inst4|counter[1]
--operation mode is normal

D1_counter[1]_lut_out = D1_counter[0] $ D1_counter[1];
D1_counter[1] = DFFEAS(D1_counter[1]_lut_out, C1_inst4, reset, , , , , , );


--D1_counter[2] is i2c_t:inst4|counter[2]
--operation mode is normal

D1_counter[2]_lut_out = D1_counter[2] $ (D1_counter[0] & D1_counter[1]);
D1_counter[2] = DFFEAS(D1_counter[2]_lut_out, C1_inst4, reset, , , , , , );


--D1_counter[3] is i2c_t:inst4|counter[3]
--operation mode is normal

D1_counter[3]_lut_out = D1_counter[3] $ (D1_counter[0] & D1_counter[1] & D1_counter[2]);
D1_counter[3] = DFFEAS(D1_counter[3]_lut_out, C1_inst4, reset, , , , , , );


--B1_link is i2c_test:inst|link
--operation mode is normal

B1_link_lut_out = B1_main_state[0] & B1L259 # !B1_main_state[0] & (B1_main_state[1] & B1L265);
B1_link = DFFEAS(B1_link_lut_out, clk, reset, , , , , , );


--B1L1 is i2c_test:inst|add~543
--operation mode is arithmetic