i2c.tan.rpt

vhdl的很多例子

; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; i2c_test:inst|readData_reg[0] ; i2c_test:inst|qout[1]         ; clk        ; clk      ; 70           ;
; Total number of failed paths ;                                          ;               ;                                                ;                               ;                               ;            ;          ; 70           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; write           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                           ; To                             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 75.11 MHz ( period = 13.313 ns )                    ; i2c_test:inst|inner_state[0]                                                                                   ; i2c_test:inst|sda_buf          ; clk        ; clk      ; None                        ; None                      ; 12.604 ns               ;
; N/A                                     ; 77.33 MHz ( period = 12.932 ns )                    ; i2c_test:inst|phase3                                                                                           ; i2c_test:inst|sda_buf          ; clk        ; clk      ; None                        ; None                      ; 12.223 ns               ;
; N/A                                     ; 77.64 MHz ( period = 12.880 ns )                    ; i2c_t:inst4|counter[0]                                                                                         ; i2c_test:inst|writeData_reg[0] ; clk        ; clk      ; None                        ; None                      ; 1.845 ns                ;
; N/A                                     ; 77.81 MHz ( period = 12.852 ns )                    ; i2c_t:inst4|counter[2]                                                                                         ; i2c_test:inst|writeData_reg[2] ; clk        ; clk      ; None                        ; None                      ; 1.817 ns                ;
; N/A                                     ; 78.33 MHz ( period = 12.767 ns )                    ; i2c_test:inst|inner_state[1]                                                                                   ; i2c_test:inst|sda_buf          ; clk        ; clk      ; None                        ; None                      ; 12.058 ns               ;
; N/A                                     ; 78.78 MHz ( period = 12.693 ns )                    ; i2c_t:inst4|counter[1]                                                                                         ; i2c_test:inst|writeData_reg[1] ; clk        ; clk      ; None                        ; None                      ; 1.658 ns                ;