lcd_vhdl.fit.rpt

vhdl的很多例子

+---------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 7.68) ; Number of LABs  (Total = 22) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 3                            ;
; 2                                           ; 1                            ;
; 3                                           ; 1                            ;
; 4                                           ; 0                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 2                            ;
; 8                                           ; 2                            ;
; 9                                           ; 0                            ;
; 10                                          ; 8                            ;
; 11                                          ; 2                            ;
; 12                                          ; 2                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 4.86) ; Number of LABs  (Total = 22) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 4                            ;
; 2                                               ; 2                            ;
; 3                                               ; 2                            ;
; 4                                               ; 3                            ;
; 5                                               ; 3                            ;
; 6                                               ; 1                            ;
; 7                                               ; 1                            ;
; 8                                               ; 2                            ;
; 9                                               ; 3                            ;
; 10                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 9.41) ; Number of LABs  (Total = 22) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 1                            ;
; 3                                           ; 2                            ;
; 4                                           ; 3                            ;
; 5                                           ; 0                            ;
; 6                                           ; 3                            ;
; 7                                           ; 0                            ;
; 8                                           ; 1                            ;
; 9                                           ; 1                            ;
; 10                                          ; 2                            ;
; 11                                          ; 2                            ;
; 12                                          ; 2                            ;
; 13                                          ; 0                            ;
; 14                                          ; 1                            ;
; 15                                          ; 0                            ;
; 16                                          ; 0                            ;
; 17                                          ; 2                            ;
; 18                                          ; 1                            ;
; 19                                          ; 0                            ;
; 20                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Nov 20 02:32:02 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LCD_VHDL -c LCD_VHDL
Info: Selected device EPM1270T144C5 for design "LCD_VHDL"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "lcd:inst|clk_int" to use Global clock
    Info: Destination "lcd:inst|clk_int" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "lcd:inst|clkdiv" to use Global clock
    Info: Destination "lcd:inst|clkdiv" may be non-global or may not use global clock
Info: Automatically promoted signal "reset" to use Global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:07
Info: Estimated most critical path is register to pin delay of 21.708 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y5; Fanout = 4; REG Node = 'lcd:inst|state[9]'
    Info: 2: + IC(0.446 ns) + CELL(0.914 ns) = 1.360 ns; Loc. = LAB_X12_Y5; Fanout = 1; COMB Node = 'lcd:inst|Equal~1130'
    Info: 3: + IC(1.592 ns) + CELL(0.914 ns) = 3.866 ns; Loc. = LAB_X12_Y4; Fanout = 16; COMB Node = 'lcd:inst|Equal~1131'
    Info: 4: + IC(0.269 ns) + CELL(0.914 ns) = 5.049 ns; Loc. = LAB_X12_Y4; Fanout = 10; COMB Node = 'lcd:inst|char_addr~1694'
    Info: 5: + IC(2.166 ns) + CELL(0.200 ns) = 7.415 ns; Loc. = LAB_X10_Y4; Fanout = 2; COMB Node = 'lcd:inst|add~1337'
    Info: 6: + IC(0.983 ns) + CELL(0.200 ns) = 8.598 ns; Loc. = LAB_X10_Y4; Fanout = 1; COMB Node = 'lcd:inst|char_addr[5]~1700'
    Info: 7: + IC(0.983 ns) + CELL(0.200 ns) = 9.781 ns; Loc. = LAB_X10_Y4; Fanout = 1; COMB Node = 'lcd:inst|char_addr[5]~1701'
    Info: 8: + IC(0.983 ns) + CELL(0.200 ns) = 10.964 ns; Loc. = LAB_X10_Y4; Fanout = 5; COMB Node = 'lcd:inst|char_addr[5]~1702'
    Info: 9: + IC(2.261 ns) + CELL(0.200 ns) = 13.425 ns; Loc. = LAB_X11_Y8; Fanout = 4; COMB Node = 'lcd:inst|data~1164'
    Info: 10: + IC(1.452 ns) + CELL(0.914 ns) = 15.791 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'lcd:inst|data~1186'
    Info: 11: + IC(0.443 ns) + CELL(0.740 ns) = 16.974 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'lcd:inst|data~1187'
    Info: 12: + IC(2.412 ns) + CELL(2.322 ns) = 21.708 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'lcd_data[6]'
    Info: Total cell delay = 7.718 ns ( 35.55 % )
    Info: Total interconnect delay = 13.990 ns ( 64.45 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 3%
Info: Fitter routing operations ending: elapsed time is 00:00:06
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Nov 20 02:32:19 2006
    Info: Elapsed time: 00:00:19