lcd_vhdl.map.rpt

vhdl的很多例子

+----------------------------------+-----------------+------------------------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 169   ;
;     -- Combinational with no register       ; 126   ;
;     -- Register only                        ; 17    ;
;     -- Combinational with a register        ; 26    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 90    ;
;     -- 3 input functions                    ; 13    ;
;     -- 2 input functions                    ; 41    ;
;     -- 1 input functions                    ; 7     ;
;     -- 0 input functions                    ; 1     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 133   ;
;     -- arithmetic mode                      ; 36    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 7     ;
;     -- asynchronous clear/load mode         ; 43    ;
;                                             ;       ;
; Total registers                             ; 43    ;
; Total logic cells in carry chains           ; 40    ;
; I/O pins                                    ; 13    ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 43    ;
; Total fan-out                               ; 629   ;
; Average fan-out                             ; 3.46  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                              ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name            ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------+
; |LCD_VHDL                  ; 169 (0)     ; 43           ; 0          ; 13   ; 0            ; 126 (0)      ; 17 (0)            ; 26 (0)           ; 40 (0)          ; 0 (0)      ; |LCD_VHDL                      ;
;    |lcd:inst|              ; 169 (159)   ; 43           ; 0          ; 0    ; 0            ; 126 (116)    ; 17 (17)           ; 26 (26)          ; 40 (40)         ; 0 (0)      ; |LCD_VHDL|lcd:inst             ;
;       |char_ram:aa|        ; 10 (10)     ; 0            ; 0          ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |LCD_VHDL|lcd:inst|char_ram:aa ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 43    ;
; Number of registers using Synchronous Clear  ; 7     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 43    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 12    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |LCD_VHDL|lcd:inst|div_counter[0] ;
; 6:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; Yes        ; |LCD_VHDL|lcd:inst|counter[0]     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |LCD_VHDL|lcd:inst|char_addr[5]   ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |LCD_VHDL|lcd:inst|char_addr[3]   ;
; 8:1                ; 7 bits    ; 35 LEs        ; 35 LEs               ; 0 LEs                  ; No         ; |LCD_VHDL|lcd:inst|data~29        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/LCD_VHDL/LCD_VHDL.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Nov 20 02:31:46 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_VHDL -c LCD_VHDL
Info: Found 1 design units, including 1 entities, in source file LCD_VHDL.bdf
    Info: Found entity 1: LCD_VHDL
Info: Found 2 design units, including 1 entities, in source file lcd.vhd
    Info: Found design unit 1: lcd-Behavioral
    Info: Found entity 1: lcd
Info: Elaborating entity "LCD_VHDL" for the top level hierarchy
Warning: Port "lcd_e" of type lcd and instance "inst" is missing source signal
Info: Elaborating entity "lcd" for hierarchy "lcd:inst"
Warning: Using design file char_ram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: char_ram-fun
    Info: Found entity 1: char_ram
Info: Elaborating entity "char_ram" for hierarchy "lcd:inst|char_ram:aa"
Warning: Reduced register "lcd:inst|state[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:inst|state[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:inst|state[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:inst|state[1]" with stuck data_in port to stuck value GND
Info: Implemented 182 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 11 output pins
    Info: Implemented 169 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Mon Nov 20 02:31:59 2006
    Info: Elapsed time: 00:00:15