tt.map.eqn

vhdl的很多例子

--operation mode is normal

J1L50 = !P1L4 & (J1L40 # P8L4 & P8L7);


--P1L7 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~57
--operation mode is arithmetic

P1L7_carry_eqn = P1L10;
P1L7 = P1L7_carry_eqn $ (!J1L40 & !J1L39);

--P1L8 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~59
--operation mode is arithmetic

P1L8 = CARRY(!P1L10 & (J1L40 # J1L39));


--J1L49 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[53]~16
--operation mode is normal

J1L49 = P1L4 & P1L7;


--P2L5 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58
--operation mode is arithmetic

P2L5 = CARRY(!P2L7 & (J1L48 # J1L47));


--LB2L15 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~187
--operation mode is arithmetic

LB2L15_carry_eqn = LB2L27;
LB2L15 = GB1L18 $ GB1L3 $ LB2L15_carry_eqn;

--LB2L16 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~189
--operation mode is arithmetic

LB2L16 = CARRY(GB1L18 & !GB1L3 & !LB2L27 # !GB1L18 & (!LB2L27 # !GB1L3));


--V1_add_sub_cella[2] is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_qe8:add_sub_6|add_sub_cella[2]
--operation mode is arithmetic

V1_add_sub_cella[2] = LB2L15;

--V1L3 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_qe8:add_sub_6|add_sub_cella[2]~COUT
--operation mode is arithmetic

V1L3 = CARRY(LB2L15);


--W3L4 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~68
--operation mode is normal

W3L4_carry_eqn = W3L14;
W3L4 = !W3L4_carry_eqn;


--T1L14 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[59]~1511
--operation mode is normal

T1L14 = !W3L4 & (V1L4 & (!V1_add_sub_cella[2]) # !V1L4 & LB2L15);


--W3L5 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~73
--operation mode is arithmetic

W3L5_carry_eqn = W3L16;
W3L5 = W3L5_carry_eqn $ (!T1L1 & !T1L2);

--W3L6 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~75
--operation mode is arithmetic

W3L6 = CARRY(!T1L1 & !T1L2 & !W3L16);


--T1L26 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[68]~1512
--operation mode is normal

T1L26 = !W4L4 & (T1L14 # W3L4 & W3L5);


--W4L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~79
--operation mode is arithmetic

W4L7_carry_eqn = W4L14;
W4L7 = W4L7_carry_eqn $ (T1L14 # T1L13);

--W4L8 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~81
--operation mode is arithmetic

W4L8 = CARRY(T1L14 # T1L13 # !W4L14);


--T1L38 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[77]~1513
--operation mode is normal

T1L38 = !W5L4 & (T1L26 # W4L4 & W4L7);


--W5L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~79
--operation mode is arithmetic

W5L7_carry_eqn = W5L12;
W5L7 = W5L7_carry_eqn $ (T1L26 # T1L25);

--W5L8 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~81
--operation mode is arithmetic

W5L8 = CARRY(!T1L26 & !T1L25 # !W5L12);


--T1L52 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[86]~1514
--operation mode is normal

T1L52 = !W1L4 & (T1L38 # W5L4 & W5L7);


--W1L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_10|add_sub_cella[3]~79
--operation mode is arithmetic

W1L7_carry_eqn = W1L10;
W1L7 = W1L7_carry_eqn $ (!T1L38 & !T1L37);

--W1L8 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_10|add_sub_cella[3]~81
--operation mode is arithmetic

W1L8 = CARRY(!W1L10 & (T1L38 # T1L37));


--T1L51 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[86]~25
--operation mode is normal

T1L51 = W1L4 & W1L7;


--W2L5 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_11|add_sub_cella[3]~80
--operation mode is arithmetic

W2L5 = CARRY(!W2L7 & (T1L50 # T1L49));


--B1_data_reg[6] is ADC_TLC549:inst|data_reg[6]
--operation mode is normal

B1_data_reg[6]_lut_out = B1_data_reg[5];
B1_data_reg[6] = DFFEAS(B1_data_reg[6]_lut_out, B1_AD_CLK_r, VCC, , B1L63, , , , );


--B1_data_reg[1] is ADC_TLC549:inst|data_reg[1]
--operation mode is normal

B1_data_reg[1]_lut_out = B1_data_reg[0];
B1_data_reg[1] = DFFEAS(B1_data_reg[1]_lut_out, B1_AD_CLK_r, VCC, , B1L63, , , , );


--B1_data_reg[0] is ADC_TLC549:inst|data_reg[0]
--operation mode is normal

B1_data_reg[0]_lut_out = ad_data;
B1_data_reg[0] = DFFEAS(B1_data_reg[0]_lut_out, B1_AD_CLK_r, VCC, , B1L63, , , , );


--B1_data_reg[2] is ADC_TLC549:inst|data_reg[2]
--operation mode is normal

B1_data_reg[2]_lut_out = B1_data_reg[1];
B1_data_reg[2] = DFFEAS(B1_data_reg[2]_lut_out, B1_AD_CLK_r, VCC, , B1L63, , , , );


--GB1L5 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][7]~1068
--operation mode is normal

GB1L5 = B1_data_out[1] $ B1_data_out[0];


--LB2L18 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~194
--operation mode is arithmetic

LB2L18 = CARRY(B1_data_out[4] & B1_data_out[0]);


--CB1L9 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~95
--operation mode is arithmetic

CB1L9_carry_eqn = CB1L12;
CB1L9 = LB2L19 $ (!CB1L9_carry_eqn);

--CB1L10 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~97
--operation mode is arithmetic

CB1L10 = CARRY(LB2L19 & (!CB1L12));


--GB1_romout[1][14] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[1][14]
--operation mode is normal

GB1_romout[1][14] = B1_data_out[7] & (!B1_data_out[5] # !B1_data_out[6]) # !B1_data_out[7] & B1_data_out[4] & B1_data_out[6] & B1_data_out[5];


--LB2L19 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~197
--operation mode is arithmetic

LB2L19_carry_eqn = LB2L22;
LB2L19 = GB1L20 $ (LB2L19_carry_eqn);

--LB2L20 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~199
--operation mode is arithmetic

LB2L20 = CARRY(!LB2L22 # !GB1L20);


--AB1L11 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[107]~46
--operation mode is normal

AB1L11 = LB2L11 & (!CB1L4);


--AB1L12 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[107]~57
--operation mode is normal

AB1L12 = CB1L4 & CB1L5;


--DB1L9 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~105
--operation mode is arithmetic

DB1L9_carry_eqn = DB1L12;
DB1L9 = DB1L9_carry_eqn $ (AB1L9 # AB1L10);

--DB1L10 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~107
--operation mode is arithmetic

DB1L10 = CARRY(!AB1L9 & !AB1L10 # !DB1L12);


--AB1L28 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[118]~729
--operation mode is normal

AB1L28 = !DB1L4 & (CB1L4 & CB1L9 # !CB1L4 & (LB2L19));


--AB1L27 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[118]~35
--operation mode is normal

AB1L27 = DB1L4 & DB1L9;


--C1L69 is bin27seg:inst1|datain[3][0]~101
--operation mode is arithmetic

C1L69 = CARRY(!AB1L26 & !AB1L25 # !C1L70);


--V1L5 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~63
--operation mode is arithmetic

V1L5_carry_eqn = V1L14;
V1L5 = LB2L21 $ (!V1L5_carry_eqn);

--V1L6 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~65
--operation mode is arithmetic

V1L6 = CARRY(!LB2L21 & (!V1L14));


--LB2L21 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~202
--operation mode is arithmetic

LB2L21_carry_eqn = LB2L16;
LB2L21 = GB1L19 $ (!LB2L21_carry_eqn);

--LB2L22 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~204
--operation mode is arithmetic

LB2L22 = CARRY(GB1L19 & (!LB2L16));


--T1L16 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[60]~1515
--operation mode is normal

T1L16 = !W3L4 & (V1L4 & V1L5 # !V1L4 & (LB2L21));


--W3L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~78
--operation mode is arithmetic

W3L7_carry_eqn = W3L6;
W3L7 = W3L7_carry_eqn $ (T1L3 # T1L4);

--W3L8 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~80
--operation mode is arithmetic

W3L8 = CARRY(T1L3 # T1L4 # !W3L6);


--T1L28 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[69]~1516
--operation mode is normal

T1L28 = !W4L4 & (T1L16 # W3L4 & W3L7);


--W4L9 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~84
--operation mode is arithmetic

W4L9_carry_eqn = W4L8;
W4L9 = W4L9_carry_eqn $ (T1L16 # T1L15);

--W4L10 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~86
--operation mode is arithmetic

W4L10 = CARRY(!T1L16 & !T1L15 # !W4L8);


--T1L40 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[78]~1517
--operation mode is normal

T1L40 = !W5L4 & (T1L28 # W4L4 & W4L9);


--W5L9 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~84
--operation mode is arithmetic

W5L9_carry_eqn = W5L8;
W5L9 = W5L9_carry_eqn $ (!T1L28 & !T1L27);

--W5L10 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~86
--operation mode is arithmetic

W5L10 = CARRY(!W5L8 & (T1L28 # T1L27));


--T1L39 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|StageOut[78]~41
--operation mode is normal

T1L39 = W5L4 & W5L9;


--P25L5 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~54
--operation mode is arithmetic

P25L5_carry_eqn = P25L8;
P25L5 = W3L4 $ (!P25L5_carry_eqn);

--P25L6 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~56
--operation mode is arithmetic

P25L6 = CARRY(!W3L4 & (!P25L8));


--J3L12 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[53]~461
--operation mode is normal

J3L12 = !P18L4 & (P25L12 & P25L5 # !P25L12 & (W3L4));


--P18L