tt.map.eqn

vhdl的很多例子

--GB1_romout[0][8] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][8]
--operation mode is normal

GB1_romout[0][8] = B1_data_out[2] $ (B1_data_out[1] # B1_data_out[0]);


--LB2L10 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~174
--operation mode is arithmetic

LB2L10 = CARRY(B1_data_out[5] & !GB1L5 & !LB2L18 # !B1_data_out[5] & (!LB2L18 # !GB1L5));


--CB1L5 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~85
--operation mode is arithmetic

CB1L5_carry_eqn = CB1L10;
CB1L5 = LB2L11 $ (CB1L5_carry_eqn);

--CB1L6 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~87
--operation mode is arithmetic

CB1L6 = CARRY(!CB1L10 # !LB2L11);


--LB2L11 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177
--operation mode is arithmetic

LB2L11_carry_eqn = LB2L20;
LB2L11 = GB1_romout[1][14] $ (!LB2L11_carry_eqn);

--LB2L12 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179
--operation mode is arithmetic

LB2L12 = CARRY(GB1_romout[1][14] & (!LB2L20));


--AB1L30 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[119]~728
--operation mode is normal

AB1L30 = !DB1L4 & (CB1L4 & CB1L5 # !CB1L4 & (LB2L11));


--DB1L5 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~95
--operation mode is arithmetic

DB1L5_carry_eqn = DB1L10;
DB1L5 = DB1L5_carry_eqn $ (!AB1L11 & !AB1L12);

--DB1L6 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~97
--operation mode is arithmetic

DB1L6 = CARRY(!DB1L10 & (AB1L11 # AB1L12));


--AB1L29 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[119]~34
--operation mode is normal

AB1L29 = DB1L4 & DB1L5;


--C1L68 is bin27seg:inst1|datain[3][0]~96
--operation mode is arithmetic

C1L68 = CARRY(!C1L69 & (AB1L28 # AB1L27));


--W1L6 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_10|add_sub_cella[3]~76
--operation mode is arithmetic

W1L6 = CARRY(!T1L40 & !T1L39 & !W1L8);


--P19L10 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63
--operation mode is arithmetic

P19L10 = CARRY(!J3L12 & !J3L11 & !P19L8);


--P1L6 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~54
--operation mode is arithmetic

P1L6 = CARRY(!J1L42 & !J1L41 & !P1L8);


--P10L10 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63
--operation mode is arithmetic

P10L10 = CARRY(!J2L30 & !J2L29 & !P10L8);


--B1_data_out[7] is ADC_TLC549:inst|data_out[7]
--operation mode is normal

B1_data_out[7]_lut_out = B1_data_reg[7];
B1_data_out[7] = DFFEAS(B1_data_out[7]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--B1_data_out[3] is ADC_TLC549:inst|data_out[3]
--operation mode is normal

B1_data_out[3]_lut_out = B1_data_reg[3];
B1_data_out[3] = DFFEAS(B1_data_out[3]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--GB1_romout[0][9] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][9]
--operation mode is normal

GB1_romout[0][9] = B1_data_out[3] $ (!B1_data_out[0] & (B1_data_out[2] # B1_data_out[1]));


--P27L10 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63
--operation mode is arithmetic

P27L10 = CARRY(!J4L48 & !J4L47 & !P27L8);


--DB1L8 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~102
--operation mode is arithmetic

DB1L8 = CARRY(!AB1L13 & !AB1L14 & !DB1L6);


--P10L12 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68
--operation mode is arithmetic

P10L12 = CARRY(P10L13);


--P9L8 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58
--operation mode is arithmetic

P9L8 = CARRY(!J2L24 & !J2L23 & !P9L12);


--P8L6 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~54
--operation mode is arithmetic

P8L6 = CARRY(!J1L36 & !J1L35 & !P8L10);


--P19L12 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68
--operation mode is arithmetic

P19L12 = CARRY(P19L13);


--P18L8 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58
--operation mode is arithmetic

P18L8 = CARRY(!J3L5 & !J3L6 & !P18L12);


--W5L6 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~76
--operation mode is arithmetic

W5L6 = CARRY(!T1L30 & !T1L29 & !W5L10);


--P27L12 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68
--operation mode is arithmetic

P27L12 = CARRY(P27L13);


--P26L8 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58
--operation mode is arithmetic

P26L8 = CARRY(!J4L42 & !J4L41 & !P26L12);


--B1_data_out[4] is ADC_TLC549:inst|data_out[4]
--operation mode is normal

B1_data_out[4]_lut_out = B1_data_reg[4];
B1_data_out[4] = DFFEAS(B1_data_out[4]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--GB1_romout[0][10] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][10]
--operation mode is normal

GB1_romout[0][10] = B1_data_out[0] & (B1_data_out[3] $ B1_data_out[1]) # !B1_data_out[0] & !B1_data_out[1] & (B1_data_out[2] # B1_data_out[3]);


--CB1L7 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~90
--operation mode is arithmetic

CB1L7_carry_eqn = CB1L6;
CB1L7 = LB2L25 $ (!CB1L7_carry_eqn);

--CB1L8 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~92
--operation mode is arithmetic

CB1L8 = CARRY(LB2L25 & (!CB1L6));


--W4L6 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~76
--operation mode is arithmetic

W4L6 = CARRY(!T1L20 & !T1L19 & !W4L12);


--V1L4 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~58
--operation mode is normal

V1L4_carry_eqn = V1L12;
V1L4 = V1L4_carry_eqn;


--P25L4 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48
--operation mode is normal

P25L4_carry_eqn = P25L6;
P25L4 = !P25L4_carry_eqn;


--J3L1 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[46]~23
--operation mode is normal

J3L1 = W4L4 & (!P25L12);


--J3L2 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[46]~28
--operation mode is normal

J3L2 = P25L12 & (!P25_add_sub_cella[1]);


--P18L10 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~63
--operation mode is arithmetic

P18L10 = CARRY(P18L13);


--P7L6 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~54
--operation mode is arithmetic

P7L6 = CARRY(!J1L30 & !J1L29 & !P7L10);


--P16L6 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53
--operation mode is arithmetic

P16L6 = CARRY(!J2L18 & !J2L17 & !P16L10);


--J2L19 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[46]~23
--operation mode is normal

J2L19 = P7L4 & (!P16L4);


--J2L20 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[46]~28
--operation mode is normal

J2L20 = P16L4 & (!P16_add_sub_cella[1]);


--P9L10 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~63
--operation mode is arithmetic

P9L10 = CARRY(P9L13);


--B1_data_out[5] is ADC_TLC549:inst|data_out[5]
--operation mode is normal

B1_data_out[5]_lut_out = B1_data_reg[5];
B1_data_out[5] = DFFEAS(B1_data_out[5]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--GB1L14 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[1][7]~1067
--operation mode is normal

GB1L14 = B1_data_out[4] $ B1_data_out[5];


--GB1_romout[0][11] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][11]
--operation mode is normal

GB1_romout[0][11] = B1_data_out[3] & (B1_data_out[1] $ B1_data_out[0] $ !B1_data_out[2]) # !B1_data_out[3] & (B1_data_out[0] & (!B1_data_out[2]) # !B1_data_out[0] & B1_data_out[1] & B1_data_out[2]);


--P33L6 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53
--operation mode is arithmetic

P33L6 = CARRY(!J4L36 & !J4L35 & !P33L10);


--J4L37 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[46]~23
--operation mode is normal

J4L37 = LB2L7 & (!P33L4);


--J4L38 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[46]~28
--operation mode is normal

J4L38 = P33L4 & (!P33_add_sub_cella[1]);


--P26L10 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~63
--operation mode is arithmetic

P26L10 = CARRY(P26L13);


--C1_count[9] is bin27seg:inst1|count[9]
--operation mode is arithmetic

C1_count[9]_carry_eqn = C1L38;
C1_count[9]_lut_out = C1_count[9] $ (C1_count[9]_carry_eqn);
C1_count[9] = DFFEAS(C1_count[9]_lut_out, clk, VCC, , , , , , );

--C1L40 is bin27seg:inst1|count[9]~280
--operation mode is arithmetic

C1L40 = CARRY(!C1L38 # !C1_count[9]);


--LB2L13 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~182
--operation mode is arithmetic

LB2L13_carry_eqn = LB2L8;
LB2L13 = GB1L15 $ GB1_romout[0][12] $ !LB2L13_carry_eqn;

--LB2L14 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~184
--operation mode is arithmetic

LB2L14 = CARRY(GB1L15 & (GB1_romout[0][12] # !LB2L8) # !GB1L15 & GB1_romout[0][12] & !LB2L8);


--P7_add_sub_cella[1] is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]
--operation mode is arithmetic

P7_add_sub_cella[1] = LB2L13;

--P7L3 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT
--operation mode is arithmetic

P7L3 = CARRY(LB2L13);


--J1L40 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[47]~1203
--operation mode is normal

J1L40 = !P8L4 & (P7L4 & (!P7_add_sub_cella[1]) # !P7L4 & LB2L13);


--P8L7 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~57
--operation mode is arithmetic

P8L7_carry_eqn = P8L12;
P8L7 = P8L7_carry_eqn $ (!J1L31 & !J1L32);

--P8L8 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~59
--operation mode is arithmetic

P8L8 = CARRY(!J1L31 & !J1L32 & !P8L12);


--J1L50 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[53]~1204