tt.map.eqn

vhdl的很多例子

--P19L5 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~51
--operation mode is arithmetic

P19L5_carry_eqn = P19L12;
P19L5 = P19L5_carry_eqn $ (!J3L7 & !J3L8);

--P19L6 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53
--operation mode is arithmetic

P19L6 = CARRY(!J3L7 & !J3L8 & !P19L12);


--P18L4 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~46
--operation mode is normal

P18L4_carry_eqn = P18L8;
P18L4 = !P18L4_carry_eqn;


--P18_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]
--operation mode is arithmetic

P18_add_sub_cella[1] = W5L4;

--P18L3 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUT
--operation mode is arithmetic

P18L3 = CARRY(W5L4);


--J3L8 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~18
--operation mode is normal

J3L8 = P18L4 & (!P18_add_sub_cella[1]);


--W5L4 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~69
--operation mode is normal

W5L4_carry_eqn = W5L6;
W5L4 = !W5L4_carry_eqn;


--J3L7 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~13
--operation mode is normal

J3L7 = W5L4 & (!P18L4);


--P27L5 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~51
--operation mode is arithmetic

P27L5_carry_eqn = P27L12;
P27L5 = P27L5_carry_eqn $ (!J4L43 & !J4L44);

--P27L6 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53
--operation mode is arithmetic

P27L6 = CARRY(!J4L43 & !J4L44 & !P27L12);


--P26L4 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~46
--operation mode is normal

P26L4_carry_eqn = P26L8;
P26L4 = !P26L4_carry_eqn;


--P26_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]
--operation mode is arithmetic

P26_add_sub_cella[1] = LB2L5;

--P26L3 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[1]~COUT
--operation mode is arithmetic

P26L3 = CARRY(LB2L5);


--J4L44 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~18
--operation mode is normal

J4L44 = P26L4 & (!P26_add_sub_cella[1]);


--LB2L5 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~162
--operation mode is arithmetic

LB2L5_carry_eqn = LB2L4;
LB2L5 = B1_data_out[4] $ GB1_romout[0][10] $ !LB2L5_carry_eqn;

--LB2L6 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~164
--operation mode is arithmetic

LB2L6 = CARRY(B1_data_out[4] & (GB1_romout[0][10] # !LB2L4) # !B1_data_out[4] & GB1_romout[0][10] & !LB2L4);


--J4L43 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[51]~13
--operation mode is normal

J4L43 = LB2L5 & (!P26L4);


--CB1L4 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~80
--operation mode is normal

CB1L4_carry_eqn = CB1L8;
CB1L4 = CB1L4_carry_eqn;


--P19L7 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~56
--operation mode is arithmetic

P19L7_carry_eqn = P19L6;
P19L7 = P19L7_carry_eqn $ (!J3L10 & !J3L9);

--P19L8 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58
--operation mode is arithmetic

P19L8 = CARRY(!P19L6 & (J3L10 # J3L9));


--W4L4 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~69
--operation mode is normal

W4L4_carry_eqn = W4L6;
W4L4 = !W4L4_carry_eqn;


--P25_cout is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|cout
--operation mode is arithmetic

P25_cout = CARRY(V1L4 & P25L4);


--P25_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]
--operation mode is arithmetic

P25_add_sub_cella[1] = W4L4;

--P25L3 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

P25L3 = CARRY(W4L4);


--J3L10 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~459
--operation mode is normal

J3L10 = !P18L4 & (P25L12 & (!P25_add_sub_cella[1]) # !P25L12 & W4L4);


--P18L5 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~51
--operation mode is arithmetic

P18L5_carry_eqn = P18L10;
P18L5 = P18L5_carry_eqn $ (!J3L1 & !J3L2);

--P18L6 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53
--operation mode is arithmetic

P18L6 = CARRY(!J3L1 & !J3L2 & !P18L10);


--J3L9 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~17
--operation mode is normal

J3L9 = P18L4 & P18L5;


--P10L7 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~56
--operation mode is arithmetic

P10L7_carry_eqn = P10L6;
P10L7 = P10L7_carry_eqn $ (!J2L28 & !J2L27);

--P10L8 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58
--operation mode is arithmetic

P10L8 = CARRY(!P10L6 & (J2L28 # J2L27));


--P7L4 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~47
--operation mode is normal

P7L4_carry_eqn = P7L6;
P7L4 = !P7L4_carry_eqn;


--P16L4 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46
--operation mode is normal

P16L4_carry_eqn = P16L6;
P16L4 = !P16L4_carry_eqn;


--P16_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]
--operation mode is arithmetic

P16_add_sub_cella[1] = P7L4;

--P16L3 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

P16L3 = CARRY(P7L4);


--J2L28 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~909
--operation mode is normal

J2L28 = !P9L4 & (P16L4 & (!P16_add_sub_cella[1]) # !P16L4 & P7L4);


--P9L5 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~51
--operation mode is arithmetic

P9L5_carry_eqn = P9L10;
P9L5 = P9L5_carry_eqn $ (!J2L19 & !J2L20);

--P9L6 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53
--operation mode is arithmetic

P9L6 = CARRY(!J2L19 & !J2L20 & !P9L10);


--J2L27 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~17
--operation mode is normal

J2L27 = P9L4 & P9L5;


--P27L7 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~56
--operation mode is arithmetic

P27L7_carry_eqn = P27L6;
P27L7 = P27L7_carry_eqn $ (!J4L46 & !J4L45);

--P27L8 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~58
--operation mode is arithmetic

P27L8 = CARRY(!P27L6 & (J4L46 # J4L45));


--LB2L7 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~167
--operation mode is arithmetic

LB2L7_carry_eqn = LB2L6;
LB2L7 = GB1L14 $ GB1_romout[0][11] $ LB2L7_carry_eqn;

--LB2L8 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~169
--operation mode is arithmetic

LB2L8 = CARRY(GB1L14 & !GB1_romout[0][11] & !LB2L6 # !GB1L14 & (!LB2L6 # !GB1_romout[0][11]));


--P33L4 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46
--operation mode is normal

P33L4_carry_eqn = P33L6;
P33L4 = !P33L4_carry_eqn;


--P33_add_sub_cella[1] is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]
--operation mode is arithmetic

P33_add_sub_cella[1] = LB2L7;

--P33L3 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

P33L3 = CARRY(LB2L7);


--J4L46 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~1359
--operation mode is normal

J4L46 = !P26L4 & (P33L4 & (!P33_add_sub_cella[1]) # !P33L4 & LB2L7);


--P26L5 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~51
--operation mode is arithmetic

P26L5_carry_eqn = P26L10;
P26L5 = P26L5_carry_eqn $ (!J4L37 & !J4L38);

--P26L6 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~53
--operation mode is arithmetic

P26L6 = CARRY(!J4L37 & !J4L38 & !P26L10);


--J4L45 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|StageOut[52]~17
--operation mode is normal

J4L45 = P26L4 & P26L5;


--B1_DCLK_DIV[0] is ADC_TLC549:inst|DCLK_DIV[0]
--operation mode is arithmetic

B1_DCLK_DIV[0]_lut_out = !B1_DCLK_DIV[0];
B1_DCLK_DIV[0] = DFFEAS(B1_DCLK_DIV[0]_lut_out, clk, VCC, , , , , B1L41, );

--B1L17 is ADC_TLC549:inst|DCLK_DIV[0]~209
--operation mode is arithmetic

B1L17 = CARRY(B1_DCLK_DIV[0]);


--C1_count[10] is bin27seg:inst1|count[10]
--operation mode is arithmetic

C1_count[10]_carry_eqn = C1L40;
C1_count[10]_lut_out = C1_count[10] $ (!C1_count[10]_carry_eqn);
C1_count[10] = DFFEAS(C1_count[10]_lut_out, clk, VCC, , , , , , );

--C1L42 is bin27seg:inst1|count[10]~276
--operation mode is arithmetic

C1L42 = CARRY(C1_count[10] & (!C1L40));


--P2L3 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~53
--operation mode is arithmetic

P2L3 = CARRY(!J1L50 & !J1L49 & !P2L5);


--W2L3 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_11|add_sub_cella[3]~75
--operation mode is arithmetic

W2L3 = CARRY(!T1L52 & !T1L51 & !W2L5);


--B1_data_out[6] is ADC_TLC549:inst|data_out[6]
--operation mode is normal

B1_data_out[6]_lut_out = B1_data_reg[6];
B1_data_out[6] = DFFEAS(B1_data_out[6]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--B1_data_out[1] is ADC_TLC549:inst|data_out[1]
--operation mode is normal

B1_data_out[1]_lut_out = B1_data_reg[1];
B1_data_out[1] = DFFEAS(B1_data_out[1]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--B1_data_out[0] is ADC_TLC549:inst|data_out[0]
--operation mode is normal

B1_data_out[0]_lut_out = B1_data_reg[0];
B1_data_out[0] = DFFEAS(B1_data_out[0]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );


--B1_data_out[2] is ADC_TLC549:inst|data_out[2]
--operation mode is normal

B1_data_out[2]_lut_out = B1_data_reg[2];
B1_data_out[2] = DFFEAS(B1_data_out[2]_lut_out, B1_AD_CLK_r, VCC, , B1L53, , , , );