tt.map.eqn

vhdl的很多例子

-- Copyright (C) 1991-2006 Altera Corporation
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--B1_AD_CLK_r is ADC_TLC549:inst|AD_CLK_r
--operation mode is normal

B1_AD_CLK_r_lut_out = B1_AD_CLK_r $ B1L41;
B1_AD_CLK_r = DFFEAS(B1_AD_CLK_r_lut_out, clk, VCC, , , , , , );


--B1_AD_CLK_EN is ADC_TLC549:inst|AD_CLK_EN
--operation mode is normal

B1_AD_CLK_EN_lut_out = B1L38 & B1_AD_CLK_EN # !B1L38 & (B1_AD_CLK_EN & !B1L42 # !B1L43);
B1_AD_CLK_EN = DFFEAS(B1_AD_CLK_EN_lut_out, B1_AD_CLK_r, VCC, , , , , , );


--B1L3 is ADC_TLC549:inst|AD_CLK~2
--operation mode is normal

B1L3 = B1_AD_CLK_r # !B1_AD_CLK_EN;


--B1_AD_CS is ADC_TLC549:inst|AD_CS
--operation mode is normal

B1_AD_CS_lut_out = !B1L38 & (B1_AD_CS # B1L42);
B1_AD_CS = DFFEAS(B1_AD_CS_lut_out, B1_AD_CLK_r, VCC, , , , , , );


--C1_count[13] is bin27seg:inst1|count[13]
--operation mode is arithmetic

C1_count[13]_carry_eqn = C1L46;
C1_count[13]_lut_out = C1_count[13] $ (C1_count[13]_carry_eqn);
C1_count[13] = DFFEAS(C1_count[13]_lut_out, clk, VCC, , , , , , );

--C1L48 is bin27seg:inst1|count[13]~260
--operation mode is arithmetic

C1L48 = CARRY(!C1L46 # !C1_count[13]);


--C1_count[12] is bin27seg:inst1|count[12]
--operation mode is arithmetic

C1_count[12]_carry_eqn = C1L44;
C1_count[12]_lut_out = C1_count[12] $ (!C1_count[12]_carry_eqn);
C1_count[12] = DFFEAS(C1_count[12]_lut_out, clk, VCC, , , , , , );

--C1L46 is bin27seg:inst1|count[12]~264
--operation mode is arithmetic

C1L46 = CARRY(C1_count[12] & (!C1L44));


--C1_count[14] is bin27seg:inst1|count[14]
--operation mode is normal

C1_count[14]_carry_eqn = C1L48;
C1_count[14]_lut_out = C1_count[14] $ (!C1_count[14]_carry_eqn);
C1_count[14] = DFFEAS(C1_count[14]_lut_out, clk, VCC, , , , , , );


--C1L1 is bin27seg:inst1|Decoder~163
--operation mode is normal

C1L1 = C1_count[13] & C1_count[12] & C1_count[14];


--C1L2 is bin27seg:inst1|Decoder~164
--operation mode is normal

C1L2 = C1_count[13] & C1_count[14] & (!C1_count[12]);


--C1L3 is bin27seg:inst1|Decoder~165
--operation mode is normal

C1L3 = C1_count[12] & C1_count[14] & (!C1_count[13]);


--C1L4 is bin27seg:inst1|Decoder~166
--operation mode is normal

C1L4 = C1_count[14] & (!C1_count[13] & !C1_count[12]);


--C1L5 is bin27seg:inst1|Decoder~167
--operation mode is normal

C1L5 = C1_count[13] & C1_count[12] & (!C1_count[14]);


--C1L6 is bin27seg:inst1|Decoder~168
--operation mode is normal

C1L6 = C1_count[13] & (!C1_count[12] & !C1_count[14]);


--C1L7 is bin27seg:inst1|Decoder~169
--operation mode is normal

C1L7 = C1_count[12] & (!C1_count[13] & !C1_count[14]);


--C1L8 is bin27seg:inst1|Decoder~170
--operation mode is normal

C1L8 = !C1_count[13] & !C1_count[12] & !C1_count[14];


--C1_datain[1][0] is bin27seg:inst1|datain[1][0]
--operation mode is normal

C1_datain[1][0]_lut_out = P2L1;
C1_datain[1][0] = DFFEAS(C1_datain[1][0]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[2][0] is bin27seg:inst1|datain[2][0]
--operation mode is normal

C1_datain[2][0]_lut_out = W2L1;
C1_datain[2][0] = DFFEAS(C1_datain[2][0]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[0][0] is bin27seg:inst1|datain[0][0]
--operation mode is normal

C1_datain[0][0]_lut_out = LB2L1;
C1_datain[0][0] = DFFEAS(C1_datain[0][0]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L9 is bin27seg:inst1|bcd_led[0]~167
--operation mode is normal

C1L9 = C1_count[12] & (C1_count[13]) # !C1_count[12] & (C1_count[13] & C1_datain[2][0] # !C1_count[13] & (C1_datain[0][0]));


--C1_datain[3][0] is bin27seg:inst1|datain[3][0]
--operation mode is normal

C1_datain[3][0]_carry_eqn = C1L67;
C1_datain[3][0]_lut_out = !C1_datain[3][0]_carry_eqn;
C1_datain[3][0] = DFFEAS(C1_datain[3][0]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L10 is bin27seg:inst1|bcd_led[0]~168
--operation mode is normal

C1L10 = C1_count[12] & (C1L9 & (C1_datain[3][0]) # !C1L9 & C1_datain[1][0]) # !C1_count[12] & (C1L9);


--C1L11 is bin27seg:inst1|bcd_led[0]~169
--operation mode is normal

C1L11 = C1L10 & (!C1_count[14]);


--C1_datain[2][1] is bin27seg:inst1|datain[2][1]
--operation mode is normal

C1_datain[2][1]_lut_out = P19L4 & (!P19_add_sub_cella[1]) # !P19L4 & W1L4;
C1_datain[2][1] = DFFEAS(C1_datain[2][1]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[1][1] is bin27seg:inst1|datain[1][1]
--operation mode is normal

C1_datain[1][1]_lut_out = P10L4 & (!P10_add_sub_cella[1]) # !P10L4 & P1L4;
C1_datain[1][1] = DFFEAS(C1_datain[1][1]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[0][1] is bin27seg:inst1|datain[0][1]
--operation mode is normal

C1_datain[0][1]_lut_out = P27L4 & (!P27_add_sub_cella[1]) # !P27L4 & LB2L3;
C1_datain[0][1] = DFFEAS(C1_datain[0][1]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L12 is bin27seg:inst1|bcd_led[1]~170
--operation mode is normal

C1L12 = C1_count[13] & (C1_count[12]) # !C1_count[13] & (C1_count[12] & C1_datain[1][1] # !C1_count[12] & (C1_datain[0][1]));


--C1_datain[3][1] is bin27seg:inst1|datain[3][1]
--operation mode is normal

C1_datain[3][1]_lut_out = DB1L4;
C1_datain[3][1] = DFFEAS(C1_datain[3][1]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L13 is bin27seg:inst1|bcd_led[1]~171
--operation mode is normal

C1L13 = C1_count[13] & (C1L12 & (C1_datain[3][1]) # !C1L12 & C1_datain[2][1]) # !C1_count[13] & (C1L12);


--C1L14 is bin27seg:inst1|bcd_led[1]~172
--operation mode is normal

C1L14 = C1L13 & (!C1_count[14]);


--C1_datain[1][2] is bin27seg:inst1|datain[1][2]
--operation mode is normal

C1_datain[1][2]_lut_out = P10L4 & P10L5 # !P10L4 & (J2L26 # J2L25);
C1_datain[1][2] = DFFEAS(C1_datain[1][2]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[2][2] is bin27seg:inst1|datain[2][2]
--operation mode is normal

C1_datain[2][2]_lut_out = P19L4 & P19L5 # !P19L4 & (J3L8 # J3L7);
C1_datain[2][2] = DFFEAS(C1_datain[2][2]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[0][2] is bin27seg:inst1|datain[0][2]
--operation mode is normal

C1_datain[0][2]_lut_out = P27L4 & P27L5 # !P27L4 & (J4L44 # J4L43);
C1_datain[0][2] = DFFEAS(C1_datain[0][2]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L15 is bin27seg:inst1|bcd_led[2]~173
--operation mode is normal

C1L15 = C1_count[12] & (C1_count[13]) # !C1_count[12] & (C1_count[13] & C1_datain[2][2] # !C1_count[13] & (C1_datain[0][2]));


--C1_datain[3][2] is bin27seg:inst1|datain[3][2]
--operation mode is normal

C1_datain[3][2]_lut_out = CB1L4;
C1_datain[3][2] = DFFEAS(C1_datain[3][2]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L16 is bin27seg:inst1|bcd_led[2]~174
--operation mode is normal

C1L16 = C1_count[12] & (C1L15 & (C1_datain[3][2]) # !C1L15 & C1_datain[1][2]) # !C1_count[12] & (C1L15);


--C1L17 is bin27seg:inst1|bcd_led[2]~175
--operation mode is normal

C1L17 = C1L16 & (!C1_count[14]);


--C1_datain[2][3] is bin27seg:inst1|datain[2][3]
--operation mode is normal

C1_datain[2][3]_lut_out = P19L4 & P19L7 # !P19L4 & (J3L10 # J3L9);
C1_datain[2][3] = DFFEAS(C1_datain[2][3]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[1][3] is bin27seg:inst1|datain[1][3]
--operation mode is normal

C1_datain[1][3]_lut_out = P10L4 & P10L7 # !P10L4 & (J2L28 # J2L27);
C1_datain[1][3] = DFFEAS(C1_datain[1][3]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1_datain[0][3] is bin27seg:inst1|datain[0][3]
--operation mode is normal

C1_datain[0][3]_lut_out = P27L4 & P27L7 # !P27L4 & (J4L46 # J4L45);
C1_datain[0][3] = DFFEAS(C1_datain[0][3]_lut_out, !B1_AD_CS, reset, , , , , , );


--C1L18 is bin27seg:inst1|bcd_led[3]~176
--operation mode is normal

C1L18 = C1_count[13] & (C1_count[12]) # !C1_count[13] & (C1_count[12] & C1_datain[1][3] # !C1_count[12] & (C1_datain[0][3]));


--C1L19 is bin27seg:inst1|bcd_led[3]~177
--operation mode is normal

C1L19 = !C1_count[14] & (C1L18 & (!C1_count[13]) # !C1L18 & C1_datain[2][3] & C1_count[13]);


--C1L83 is bin27seg:inst1|seg_data[6]~69
--operation mode is normal

C1L83 = C1L11 & (C1L19 # C1L14 $ C1L17) # !C1L11 & (C1L14 # C1L17 $ C1L19);


--C1L82 is bin27seg:inst1|seg_data[5]~70
--operation mode is normal

C1L82 = C1L11 & (C1L19 $ (C1L14 # !C1L17)) # !C1L11 & C1L14 & !C1L17 & !C1L19;


--C1L81 is bin27seg:inst1|seg_data[4]~71
--operation mode is normal

C1L81 = C1L14 & C1L11 & (!C1L19) # !C1L14 & (C1L17 & (!C1L19) # !C1L17 & C1L11);


--C1L80 is bin27seg:inst1|seg_data[3]~72
--operation mode is normal

C1L80 = C1L14 & (C1L11 & C1L17 # !C1L11 & !C1L17 & C1L19) # !C1L14 & !C1L19 & (C1L11 $ C1L17);


--C1L79 is bin27seg:inst1|seg_data[2]~73
--operation mode is normal

C1L79 = C1L17 & C1L19 & (C1L14 # !C1L11) # !C1L17 & !C1L11 & C1L14 & !C1L19;


--C1L78 is bin27seg:inst1|seg_data[1]~74
--operation mode is normal

C1L78 = C1L14 & (C1L11 & (C1L19) # !C1L11 & C1L17) # !C1L14 & C1L17 & (C1L11 $ C1L19);


--C1L77 is bin27seg:inst1|seg_data[0]~75
--operation mode is normal

C1L77 = C1L17 & !C1L14 & (C1L11 $ !C1L19) # !C1L17 & C1L11 & (C1L14 $ !C1L19);


--B1_DCLK_DIV[6] is ADC_TLC549:inst|DCLK_DIV[6]
--operation mode is arithmetic

B1_DCLK_DIV[6]_carry_eqn = B1L27;
B1_DCLK_DIV[6]_lut_out = B1_DCLK_DIV[6] $ (!B1_DCLK_DIV[6]_carry_eqn);
B1_DCLK_DIV[6] = DFFEAS(B1_DCLK_DIV[6]_lut_out, clk, VCC, , , , , B1L41, );

--B1L29 is ADC_TLC549:inst|DCLK_DIV[6]~169
--operation mode is arithmetic

B1L29 = CARRY(B1_DCLK_DIV[6] & (!B1L27));


--B1_DCLK_DIV[7] is ADC_TLC549:inst|DCLK_DIV[7]
--operation mode is arithmetic

B1_DCLK_DIV[7]_carry_eqn = B1L29;
B1_DCLK_DIV[7]_lut_out = B1_DCLK_DIV[7] $ (B1_DCLK_DIV[7]_carry_eqn);
B1_DCLK_DIV[7] = DFFEAS(B1_DCLK_DIV[7]_lut_out, clk, VCC, , , , , B1L41, );

--B1L31 is ADC_TLC549:inst|DCLK_DIV[7]~173
--operation mode is arithmetic

B1L31 = CARRY(!B1L29 # !B1_DCLK_DIV[7]);