tt.fit.eqn

vhdl的很多例子

--B1_data_out[1] is ADC_TLC549:inst|data_out[1] at LC_X15_Y11_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out[1] = DFFEAS(GB1_romout[0][8], GLOBAL(B1_AD_CLK_r), VCC, , B1L65, B1_data_reg[1], , , VCC);


--LB2L14 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~174 at LC_X15_Y11_N4
--operation mode is arithmetic

LB2L14 = CARRY(GB1L5 & !B1_data_out[5] & !LB2L25 # !GB1L5 & (!LB2L25 # !B1_data_out[5]));


--CB1L6 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~85 at LC_X19_Y8_N5
--operation mode is arithmetic

CB1L6_carry_eqn = (!CB1L13 & GND) # (CB1L13 & VCC);
CB1L6 = LB2L15 $ CB1L6_carry_eqn;

--CB1L7 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~87 at LC_X19_Y8_N5
--operation mode is arithmetic

CB1L7_cout_0 = !CB1L13 # !LB2L15;
CB1L7 = CARRY(CB1L7_cout_0);

--CB1L8 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~87COUT1_127 at LC_X19_Y8_N5
--operation mode is arithmetic

CB1L8_cout_1 = !CB1L13 # !LB2L15;
CB1L8 = CARRY(CB1L8_cout_1);


--LB2L15 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~177 at LC_X15_Y10_N5
--operation mode is arithmetic

LB2L15_carry_eqn = LB2L27;
LB2L15 = GB1_romout[1][14] $ !LB2L15_carry_eqn;

--LB2L16 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179 at LC_X15_Y10_N5
--operation mode is arithmetic

LB2L16_cout_0 = GB1_romout[1][14] & !LB2L27;
LB2L16 = CARRY(LB2L16_cout_0);

--LB2L17 is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~179COUT1_232 at LC_X15_Y10_N5
--operation mode is arithmetic

LB2L17_cout_1 = GB1_romout[1][14] & !LB2L27;
LB2L17 = CARRY(LB2L17_cout_1);


--AB1L30 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[119]~728 at LC_X24_Y10_N5
--operation mode is normal

AB1L30 = !DB1L5 & (CB1L5 & CB1L6 # !CB1L5 & (LB2L15));


--DB1L6 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~95 at LC_X21_Y9_N6
--operation mode is arithmetic

DB1L6_carry_eqn = (!DB1L16 & DB1L13) # (DB1L16 & DB1L14);
DB1L6 = DB1L6_carry_eqn $ (!AB1L12 & !AB1L11);

--DB1L7 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~97 at LC_X21_Y9_N6
--operation mode is arithmetic

DB1L7_cout_0 = !DB1L13 & (AB1L12 # AB1L11);
DB1L7 = CARRY(DB1L7_cout_0);

--DB1L8 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~97COUT1_143 at LC_X21_Y9_N6
--operation mode is arithmetic

DB1L8_cout_1 = !DB1L14 & (AB1L12 # AB1L11);
DB1L8 = CARRY(DB1L8_cout_1);


--AB1L29 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|StageOut[119]~34 at LC_X22_Y12_N0
--operation mode is normal

AB1L29 = DB1L5 & (DB1L6);


--C1L82 is bin27seg:inst1|datain[3][0]~96COUT0_149 at LC_X20_Y14_N6
--operation mode is arithmetic

C1L82_cout_0 = !C1L85 & (AB1L28 # AB1L27);
C1L82 = CARRY(C1L82_cout_0);

--C1L83 is bin27seg:inst1|datain[3][0]~96COUT1_150 at LC_X20_Y14_N6
--operation mode is arithmetic

C1L83_cout_1 = !C1L86 & (AB1L28 # AB1L27);
C1L83 = CARRY(C1L83_cout_1);


--W1L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_10|add_sub_cella[3]~76 at LC_X21_Y12_N6
--operation mode is arithmetic

W1L7_cout_0 = !T1L39 & !T1L40 & !W1L10;
W1L7 = CARRY(W1L7_cout_0);

--W1L8 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_10|add_sub_cella[3]~76COUT1_111 at LC_X21_Y12_N6
--operation mode is arithmetic

W1L8_cout_1 = !T1L39 & !T1L40 & !W1L11;
W1L8 = CARRY(W1L8_cout_1);


--P19L13 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63 at LC_X19_Y14_N8
--operation mode is arithmetic

P19L13_cout_0 = !J3L12 & !J3L11 & !P19L10;
P19L13 = CARRY(P19L13_cout_0);

--P19L14 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63COUT1_77 at LC_X19_Y14_N8
--operation mode is arithmetic

P19L14_cout_1 = !J3L12 & !J3L11 & !P19L11;
P19L14 = CARRY(P19L14_cout_1);


--P1L7 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~54 at LC_X21_Y14_N3
--operation mode is arithmetic

P1L7_cout_0 = !J1L42 & !J1L41 & !P1L10;
P1L7 = CARRY(P1L7_cout_0);

--P1L8 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~54COUT1_78 at LC_X21_Y14_N3
--operation mode is arithmetic

P1L8_cout_1 = !J1L42 & !J1L41 & !P1L11;
P1L8 = CARRY(P1L8_cout_1);


--P10L13 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63 at LC_X20_Y13_N8
--operation mode is arithmetic

P10L13_cout_0 = !J2L30 & !J2L29 & !P10L10;
P10L13 = CARRY(P10L13_cout_0);

--P10L14 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63COUT1_77 at LC_X20_Y13_N8
--operation mode is arithmetic

P10L14_cout_1 = !J2L30 & !J2L29 & !P10L11;
P10L14 = CARRY(P10L14_cout_1);


--GB1_romout[0][9] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][9] at LC_X15_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out[3]_qfbk = B1_data_out[3];
GB1_romout[0][9] = B1_data_out[3]_qfbk $ (!B1_data_out[0] & (B1_data_out[1] # B1_data_out[2]));

--B1_data_out[3] is ADC_TLC549:inst|data_out[3] at LC_X15_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out[3] = DFFEAS(GB1_romout[0][9], GLOBAL(B1_AD_CLK_r), VCC, , B1L65, B1_data_reg[3], , , VCC);


--P27L13 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63 at LC_X22_Y15_N3
--operation mode is arithmetic

P27L13_cout_0 = !J4L48 & !J4L47 & !P27L10;
P27L13 = CARRY(P27L13_cout_0);

--P27L14 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~63COUT1_77 at LC_X22_Y15_N3
--operation mode is arithmetic

P27L14_cout_1 = !J4L48 & !J4L47 & !P27L11;
P27L14 = CARRY(P27L14_cout_1);


--DB1L10 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~102 at LC_X21_Y9_N7
--operation mode is arithmetic

DB1L10_cout_0 = !AB1L13 & !AB1L14 & !DB1L7;
DB1L10 = CARRY(DB1L10_cout_0);

--DB1L11 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_5g8:add_sub_10|add_sub_cella[4]~102COUT1_144 at LC_X21_Y9_N7
--operation mode is arithmetic

DB1L11_cout_1 = !AB1L13 & !AB1L14 & !DB1L8;
DB1L11 = CARRY(DB1L11_cout_1);


--P10L16 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68 at LC_X20_Y13_N5
--operation mode is arithmetic

P10L16_cout_0 = P10L18;
P10L16 = CARRY(P10L16_cout_0);

--P10L17 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68COUT1_75 at LC_X20_Y13_N5
--operation mode is arithmetic

P10L17_cout_1 = P10L18;
P10L17 = CARRY(P10L17_cout_1);


--P9L10 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58 at LC_X19_Y13_N3
--operation mode is arithmetic

P9L10_cout_0 = !J2L24 & !J2L23 & !P9L16;
P9L10 = CARRY(P9L10_cout_0);

--P9L11 is bin27seg:inst1|lpm_divide:mod_rtl_2|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58COUT1_77 at LC_X19_Y13_N3
--operation mode is arithmetic

P9L11_cout_1 = !J2L24 & !J2L23 & !P9L17;
P9L11 = CARRY(P9L11_cout_1);


--P8L7 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~54 at LC_X21_Y13_N8
--operation mode is arithmetic

P8L7_cout_0 = !J1L36 & !J1L35 & !P8L13;
P8L7 = CARRY(P8L7_cout_0);

--P8L8 is bin27seg:inst1|lpm_divide:div_rtl_1|lpm_divide_vmf:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~54COUT1_78 at LC_X21_Y13_N8
--operation mode is arithmetic

P8L8_cout_1 = !J1L36 & !J1L35 & !P8L14;
P8L8 = CARRY(P8L8_cout_1);


--P19L16 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68 at LC_X19_Y14_N5
--operation mode is arithmetic

P19L16_cout_0 = P19L18;
P19L16 = CARRY(P19L16_cout_0);

--P19L17 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68COUT1_75 at LC_X19_Y14_N5
--operation mode is arithmetic

P19L17_cout_1 = P19L18;
P19L17 = CARRY(P19L17_cout_1);


--P18L10 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58 at LC_X19_Y11_N3
--operation mode is arithmetic

P18L10_cout_0 = !J3L5 & !J3L6 & !P18L16;
P18L10 = CARRY(P18L10_cout_0);

--P18L11 is bin27seg:inst1|lpm_divide:mod_rtl_4|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58COUT1_77 at LC_X19_Y11_N3
--operation mode is arithmetic

P18L11_cout_1 = !J3L5 & !J3L6 & !P18L17;
P18L11 = CARRY(P18L11_cout_1);


--W5L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~76 at LC_X22_Y11_N6
--operation mode is arithmetic

W5L7_cout_0 = !T1L29 & !T1L30 & !W5L14;
W5L7 = CARRY(W5L7_cout_0);

--W5L8 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~76COUT1_111 at LC_X22_Y11_N6
--operation mode is arithmetic

W5L8_cout_1 = !T1L29 & !T1L30 & !W5L15;
W5L8 = CARRY(W5L8_cout_1);


--P27L16 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68 at LC_X22_Y15_N0
--operation mode is arithmetic

P27L16_cout_0 = P27L18;
P27L16 = CARRY(P27L16_cout_0);

--P27L17 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_11|add_sub_cella[2]~68COUT1_75 at LC_X22_Y15_N0
--operation mode is arithmetic

P27L17_cout_1 = P27L18;
P27L17 = CARRY(P27L17_cout_1);


--P26L10 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58 at LC_X23_Y15_N3
--operation mode is arithmetic

P26L10_cout_0 = !J4L42 & !J4L41 & !P26L16;
P26L10 = CARRY(P26L10_cout_0);

--P26L11 is bin27seg:inst1|lpm_divide:mod_rtl_5|lpm_divide_2ff:auto_generated|sign_div_unsign_1jg:divider|alt_u_div_7od:divider|add_sub_oe8:add_sub_10|add_sub_cella[2]~58COUT1_77 at LC_X23_Y15_N3
--operation mode is arithmetic

P26L11_cout_1 = !J4L42 & !J4L41 & !P26L17;
P26L11 = CARRY(P26L11_cout_1);


--GB1_romout[0][10] is bin27seg:inst1|lpm_mult:mult_rtl_0|multcore:mult_core|romout[0][10] at LC_X15_Y11_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out[0]_qfbk = B1_data_out[0];
GB1_romout[0][10] = B1_data_out[1] & !B1_data_out[3] & B1_data_out[0]_qfbk # !B1_data_out[1] & (B1_data_out[3] # !B1_data_out[0]_qfbk & B1_data_out[2]);

--B1_data_out[0] is ADC_TLC549:inst|data_out[0] at LC_X15_Y11_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_out[0] = DFFEAS(GB1_romout[0][10], GLOBAL(B1_AD_CLK_r), VCC, , B1L65, B1_data_reg[0], , , VCC);


--CB1L9 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~90 at LC_X19_Y8_N6
--operation mode is arithmetic

CB1L9_carry_eqn = (!CB1L13 & CB1L7) # (CB1L13 & CB1L8);
CB1L9 = LB2L34 $ (!CB1L9_carry_eqn);

--CB1L10 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~92 at LC_X19_Y8_N6
--operation mode is arithmetic

CB1L10_cout_0 = LB2L34 & (!CB1L7);
CB1L10 = CARRY(CB1L10_cout_0);

--CB1L11 is bin27seg:inst1|lpm_divide:div_rtl_6|lpm_divide_cof:auto_generated|sign_div_unsign_ekg:divider|alt_u_div_1rd:divider|add_sub_4g8:add_sub_9|add_sub_cella[4]~92COUT1_128 at LC_X19_Y8_N6
--operation mode is arithmetic

CB1L11_cout_1 = LB2L34 & (!CB1L8);
CB1L11 = CARRY(CB1L11_cout_1);


--W4L7 is bin27seg:inst1|lpm_divide:div_rtl_3|lpm_divide_2nf:auto_generated|sign_div_unsign_4jg:divider|alt_u_div_dod:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~